Lsi Corporation

Sathappan Palaniappan

Dharmesh Kishor Tirthdasani

Romeshkumar Bharatkumar Mehta

Srinivasa Rao Kothamasu

Ravindra Bidnur

Jean Jacob

Deepak Ashok Naik

Priya Gururaj Kulkarni

A memory device comprises one or more power gates and state signaling circuitry. Each of the one or more power gates is configurable such that a respective portion of the memory device is powered down. The state signaling circuitry is operative to produce a power state output signal indicative of when the one or more power gates are configured such that the memory device is fully powered up.

Power gated memory device with power state indication

A data processing system comprises a processor operating according to a first clock signal and a memory operating according to a second clock signal. The data processing system causes the processor to read data from the memory at least in part in response to a signal from first synchronizing circuitry and a signal from second synchronizing circuitry. The first synchronizing circuitry comprises a first storage element that samples a signal synchronized to the second clock signal in combination with a second storage element that samples an output of the first storage element. The first and second storage elements are triggered by inverse transitions in the first clock signal. The second synchronizing circuitry comprises third and fourth storage elements configured in a similar manner, except that they sample a signal synchronized to the first clock signal and are triggered by inverse transitions in the second clock signal.

Arbitration circuitry for asynchronous memory accesses

A system and method for decoding coded data streams is disclosed. In one embodiment, in a method for decoding coded data streams, a coded data stream including an embedded input clock signal is oversampled to measure substantially sequentially a plurality of pulse widths in a current frame using a sync and reference value acquisition digital logic. The coded data steam includes a plurality of frames, and each frame includes a preamble of fixed length and a series of data bits. The oversampling is performed using a high frequency clock signal having a substantially higher frequency than a frequency of the embedded input clock signal. Then, the coded data stream is decoded based on the measured plurality of pulse widths in the current frame using a data decoder.

Method and apparatus for decoding coded data streams

A power management controller controls a power mode associated with a memory device and includes a logic element operative to provide a power mode control signal. The logic element is responsive to first and second control signals, the second control signal being a delayed version of the first control signal. The first control signal is provided by a processing device, and the power mode control signal transitions (i) inactive before a chip select signal transitions active and/or (ii) active after the chip select signal transitions inactive. The chip select signal controls the memory device, and the power mode control signal controls the power mode associated with the memory device. A corresponding method, computer-readable medium, and electronic system are also disclosed. A method that selects a power control mode associated with the power management controller, which controls a power mode associated with the memory device, is also disclosed.

Method and apparatus for power management control of an embedded memory having sleep and shutdown features

An interface device to interface a processing device and a memory device includes an error correcting code (ECC) encoder to calculate ECC bit(s) and to provide the ECC bit(s) to the processing device based at least in part on data provided by the memory device, thereby eliminating a need to store the ECC bits in the memory device. The interface device may include a parity encoder to provide parity bit(s) to the memory device as a function of data provided by the processing device, and a parity decoder to selectively modify the ECC bit(s) as a function of the data and parity bit(s) provided by the memory device. The ECC encoder may provide ECC bits, and the parity decoder may selectively modify the ECC bits provided to the processing device based on data provided by the memory device and parity bit(s) provided by the memory device.

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Bengaluru, India

Sathappan Palaniappan