Intel Corporation

Satchitanand Jain

Derrick Chu Lin

Nimish H Modi

Ramamohan Rao Vakkalagadda

Varsha P Tagare

A technique for increasing the number of physical segment registers by renaming logical segment registers into a larger register space. The remapping of the segment registers allows for instructions accessing the segment registers to be executed non-serially. The renaming of segment registers is achieved by assigning a shadow register to a segment register name. Thus, a pair of registers are physically available for a specified logical register in an instruction set to be renamed. Two bits, designated as the PSEG and SPEC bits, are used to control the remapping.

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San Jose, CA, United States of America

Satchitanand Jain