Intel Corporation

Satchit Jain

Barnes Cooper

Leslie E Cline

Sung-Soo Cho

Anil Nanduri

Debra T Cohen

Sun-Soo Cho

Siripong Sritanyaratana

An interface between an accelerated graphics port graphics controller (AGP-GC) and a core controller to prevent entry into a low power state from interfering with transfers to or from the AGP-GC that have been requested but not completed. The core controller can communicate to the AGP-GC an intent to enter a low power state, while the AGP-GC can communicate to the core controller the busy status of the AGP-GC. When the AGP-GC receives notice of an intent to enter a low power state, it can stop issuing requests to the core controller. When the core controller detects that the AGP-GC is busy, the core controller can postpone entry into the low power state until the AGP-GC completes any requests that are in progress. In an alternate use of the interface, if the AGP-GC wishes to make a request during a low power state, it can signal the core controller of this need by indicating a busy status, which can trigger the core controller to initiate an exit from the low power state.

Entering and exiting power managed states without disrupting accelerated graphics port transactions

A system has a processor with multiple states, including an awake state and a sleep state, a memory subsystem including a memory controller and memory devices, and a second memory. The system uses software in the second memory to initialize the memory controller upon a transition from a sleep state to an awake state. The system detects a wake event trigger, and in response to the wake event trigger, executes software stored in the second memory to initialize the memory controller, and then executes software out of the first memory after the initialization.

Method of initializing a memory controller by executing software in a second memory to wake up a system

A mechanism for conserving power consumption includes a processor, a memory, and a memory control hub (&ldquo;MCH&rdquo;). The memory is coupled to the processor and MCH is also coupled to the processor. MCH is further configured to switch between at least two power consumption modes for conserving power consumption.

Method and apparatus to implement the ACPI(advanced configuration and power interface) C3 state in a RDRAM based system

An integrated circuit contains a central processing unit (&ldquo;CPU&rdquo;), a graphic control hub (&ldquo;GCH&rdquo;), a memory control hub (&ldquo;MCH&rdquo;), and a phase lock loop (&ldquo;PLL&rdquo;). The GCH, MCH, and PLL are coupled to the CPU. The MCH controls memory transactions. The PLL is configured to allow the CPU to operate at more than one power consumption states.

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San Jose, CA, United States of America

Satchit Jain