Qualcomm Incorporated

Sassan Shahrokhinia

Terrence Brian Remple

Gurkanwal Singh Sahota

Nam Dang

Mehdi Hamidi Sani

Rajeev Jain

Duane Ellis

Farsheed Mahmoudi

Harshat Pant

Zhengming Fu

James Thomas Doyle

Lipeng Cao

Chuang Zhang

Yu Huang

Lam Ho

Mong Chit Wong

Victor Kam Kin Wong

Nam Van Dang

Duane Eugene Ellis

An integrated circuit is disclosed for power multiplexing with an active load. In an example aspect, the integrated circuit includes a first power rail, a second power rail, a load power rail, multiple power-multiplexer tiles, and power-multiplexer control circuitry. The first power rail is at a first voltage, and the second power rail is at a second voltage. The multiple power-multiplexer tiles are coupled in series in a chained arrangement and jointly perform a power-multiplexing operation responsive to a power-rail switching signal. Each power-multiplexer tile switches between coupling the load power rail to the first power rail and the second power rail. The power-multiplexer control circuitry is coupled to the first and second power rails and includes a comparator to produce a relative voltage signal based on the first and second voltages. The power-multiplexer control circuitry generates the power-rail switching signal based on the relative voltage signal.

Power multiplexing with an active load

An integrated circuit (IC) is disclosed herein for adaptive power multiplexing with a power distribution network. In an example aspect, the integrated circuit includes a first power rail, a second power rail, and a load power rail. The integrated circuit also includes multiple power-multiplexer tiles and power-multiplexer control circuitry. The multiple power-multiplexer tiles are coupled in series in a chained arrangement and configured to jointly perform a power-multiplexing operation. Each power-multiplexer tile is configured to switch between coupling the load power rail to the first power rail and coupling the load power rail to the second power rail. The power-multiplexer control circuitry is configured to control a direction of current flow to prevent cross-conduction between the first power rail and the second power rail during the power-multiplexing operation.

Adaptive power multiplexing with a power distribution network

A link layer to physical layer (PHY) serial interface is disclosed. In one aspect, a system on a chip (SoC) integrated circuit (IC) includes a link layer circuit, and a remote IC includes a Universal Serial Bus (USB) PHY circuit. A bus having four or fewer wires connects the two ICs. A link bridge communicates with the link layer circuit and serializes USB Transceiver Macrocell Interface (UTMI) signaling received from the link layer circuit as high speed (HS) USB messages for transmission to the remote IC. The link bridge also receives HS messages from the USB PHY circuit on the remote IC. The link bridge deserializes the HS messages to extract UTMI signaling and passes the extracted UTMI signaling to the link layer circuit.

Link layer to physical layer (PHY) serial interface

In certain aspects, a regulator includes a variable-impedance switch coupled between a supply rail and a circuit block, wherein an impedance of the variable-impedance switch is set by an impedance code input to the variable-impedance switch. The regulator also includes an analog-to-digital converter (ADC) configured to convert a block supply voltage at the circuit block into a voltage code, and a controller configured to adjust the impedance code based on the voltage code in a direction that reduces a difference between the block supply voltage and a target supply voltage.

Digital sub-regulators

Embedded Universal Serial Bus (USB) debug (EUD) for multi-interfaced debugging in electronic systems are disclosed. Electronic systems contain complex integrated circuits (ICs) that require extensive testing and debugging to ensure good quality and performance. In exemplary aspects, an EUD is provided in an electronic system. The EUD is configured to send control information to and/or collect debugging information from multiple internal debugging interfaces in the electronic system. The EUD is also configured to convert the debugging information into a USB format so that the debugging information can be externally accessed through a USB interface provided by the electronic system. The EUD can provide non-invasive monitoring of the electronic system. The electronic system is able to use a USB port for communications in a mission mode while EUD is enabled. Additionally, the electronic system can turn on or off all system clocks during power-saving mode while the EUD continues to function.

Embedded universal serial bus (USB) debug (EUD) for multi-interfaced debugging in electronic systems

An apparatus and method are disclosed for efficiently using power at a voltage regulator, such as a synchronous buck converter. The synchronous buck converter includes a first switch and a second switch operated by a first control signal and a second control signal, respectively, where the first and second control signals have a corresponding phase difference. A logic circuit measures a duty cycle of an input pulse width modulated (PWM) signal against iterative changes of the phase difference between the first control signal and the second control signal. The logic circuit selects a phase difference corresponding to a minimum value of the PWM signal, thereby optimizing dead time at the synchronous buck converter. The logic circuit may include a Digital Pulse Width Modulator.

Circuits and methods providing dead time adjustment at a synchronous buck converter

Circuitry that generates an interface signal between a first and a second integrated circuit (IC). The circuitry includes a reference circuit that provides a reference signal, an interface circuit, and a circuit element. The interface circuit is implemented on the first IC, operatively couples to the reference circuit, receives the reference signal and a data input, and generates the interface signal. The circuit element is implemented on the second IC, operatively couples to the control circuit, receives the interface signal, and provides an output signal. The reference signal can be a voltage or a current signal, and can be generated in the first or second IC. The interface circuit can be implemented with a current mirror coupled to a switch array, and can be oversampled to ease the filtering requirement. The interface signal can be a differential current signal having multiple (e.g., four, eight, or more) bits of resolution. The circuit element can be, for example, a VGA, a modulator, or other circuits.

Interface between digital and analog circuits

Method and circuit for providing interface signals between integrated circuits

Growing community of inventors

San Diego, CA, United States of America

Sassan Shahrokhinia