Kepler Computing Inc.

Intel Corporation

Cornell University

General Electric Company

Cornell Research Foundation Inc.

Intel Corporaton

Sasikanth Manipatruni

Amrita Mathuriya

Rajeev Kumar Dokania

Tanay Gosavi

Ian A Young

Noriyuki Sato

Rafael Rios

Ikenna Odinaka

Dmitri E Nikonov

Ramamoorthy Ramesh

Debo Olaosebikan

Niloy Mukherjee

Gaurav Thareja

Somilkumar J Rathi

Robert Menezes

Pratyush Pandey

Chia-Ching Lin

Kaan Oguz

Mauricio Manfrini

Ram K Krishnamurthy

Christopher B Wilkerson

Ramesh Ramamoorthy

Abhishek A Sharma

Raghavan Kumar

Gregory Kengho Chen

Phil Knag

Huseyin Ekin Sumbul

Nabil Imam

Christopher J Wiegand

Jason Y Wu

Yuan-Sheng Fang

Benjamin Buford

Darshak Doshi

Kevin O'Brien

Uygar E Avci

Michal Lipson

Angeline Smith

Anurag Chaudhry

Tofizur Rahman

James David Clarkson

Gabriel Antonio Paulius Velarde

Huichu Liu

Neal Reynolds

Fnu Atiquzzaman

Tanay Karnik

Victor W Lee

Gary Allen

Mustansir Yunus Mukadam

Brian S Doyle

Kelin J Kuhn

Daniel Henry Morris

John J Plombon

Kaushik Vaidyanathan

Jack T Kavalieros

Van H Le

Jasmeet S Chawla

Raseong Kim

Zeying Ren

Ravi Pillarisetty

Shawna M Liff

Debendra Mallik

Seiyon Kim

Hui Jae Yoo

Vivek K Singh

John C Johnson

Sou-Chi Chang

Debraj Guhabiswas

Patrick R Morrow

James S Clarke

Kevin Lai Lin

Robert L Bristol

David J Michalak

Nazila Haratipour

Chytra Pawashe

Pramod Kolar

Rajeev K Dokania

James Pellegren

Kyle Preston

Tahir Ghani

Mark L Doczy

Hong Wang

Charles C Kuo

Biswajeet Guha

Christopher Judson Hardy

Sreenivas Subramoney

Long L Chen

Yih Wang

Rajashree Raji Baskaran

Kanwaljit Singh

Jayesh Gaur

Nafees Kabir

Justin Brockman

George I Bourianoff

Md Tofizur Rahman

Qianfan Xu

Alyssa B Apsel

Paul McEuen

Ishwar Bhati

Michael Christenson

Michael Kishinevsky

Asynchronous full-adder circuit is described. The full-adder includes majority and/or minority gates some of which receive two first inputs (A.t, A.f), two second inputs (B.t, B.f), two carry inputs (Cin.t, Cin.f), third acknowledgement input (Cout.e), and fourth acknowledgement input (Sum.e), and generate controls to control gates of transistors, wherein the transistors are coupled to generate two carry outputs (Cout.t, Cout.e), two sum outputs (Sum.t, Sum.e), first acknowledgement output (A.e), second acknowledgement output (B.e), and third acknowledgement output (Cin.e). The majority and/or minority gates comprise CMOS gates or multi-input capacitive circuitries. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the asynchronous full-adder circuit. Asynchronous full-adders coupled in series is used to implement a carry-ripple adder.

Asynchronous full-adder with majority or minority gates to generate carry-out true output

A pocket integration for high density memory and logic applications and methods of fabrication are described. While various embodiments are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For example, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.

Method of fabricating memory devices using pocket integration

Described herein is a read and write scheme to improve memory reliability. In at least one embodiment, one or more circuitries are provided to perform logic 0 write operation in a first phase and logic 1 write operation in a second phase for a plurality of bit-cells controlled by a word-line. In at least one embodiment, an individual bit-cell comprises a transistor having a gate terminal coupled to the word-line; and a capacitor including non-linear polar material, wherein the capacitor has a first terminal coupled to a plate-line and a second terminal coupled to the transistor, wherein a source or drain terminal of the transistor is coupled to a bit-line.

Time decoupled write operations for non-linear polar material based memory

Asynchronous full-adder with majority or minority gates to generate carry-out false output

Asynchronous full-adder with majority or minority gates to generate sum false output

A low power adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. The adder may include minority gates and/or majority gates. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.

Ferroelectric or paraelectric wide-input minority or majority gate based low power adder

A device structure comprises a first conductive interconnect, an electrode structure on the first conductive interconnect, an etch stop layer laterally surrounding the electrode structure; a plurality of memory devices above the electrode structure, where individual ones of the plurality of memory devices comprise a dielectric layer comprising a perovskite material. The device structure further comprises a plate electrode coupled between the plurality of memory devices and the electrode structure, where the plate electrode is in direct contact with a respective lower most conductive layer of the individual ones of the plurality of memory devices. The device structure further includes an insulative hydrogen barrier layer on at least a sidewall of the individual ones of the plurality of memory devices; and a plurality of via electrodes, wherein individual ones of the plurality of via electrodes are on a respective one of the individual ones of the plurality of memory devices.

Methods of fabricating planar capacitors on a shared plate electrode

Capacitor devices with shared electrode and methods of fabrication

The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor, which in turn comprises a polar layer comprising a crystalline base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen, wherein the dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor additionally comprises first and second crystalline conductive or semiconductive oxide electrodes on opposing sides of the polar layer, wherein the polar layer has a lattice constant that is matched within about 20% of a lattice constant of one or both of the first and second crystalline conductive or semiconductive oxide electrodes. The first crystalline conductive or semiconductive oxide electrode serves as a template for growing the polar layer thereon, such that at least a portion of the polar layer is pseudomorphically formed on the first crystalline conductive or semiconductive oxide electrode.

Doped polar layers and semiconductor device incorporating same

Described herein is a memory sensing scheme that improves noise margin. In at least one embodiment, one or more circuitries are described that are coupled to a bit-cell, wherein the bit-cell is coupled to a plate-line and a bit-line, wherein the one or more circuitries are to sense a bit-value stored in the bit-cell based, at least in part, on a first floating charge on a plate-line and a second floating charge on a bit-line.

Apparatus and method to improve sensing noise margin in a non-linear polar material based bit-cell

Drain coupled non-linear polar material based capacitors for memory and logic

Methods of fabricating trench capacitors on a shared plate electrode

A multiplier cell is derived from a 1-bit full adder and an AND gate. The 1-bit full adder is derived from majority and/or minority gates. The majority and/or minority gates include non-linear polar material (e.g., ferroelectric or paraelectric material). A reset mechanism is provided to reset the nodes across the non-linear polar material. The multiplier cell is a hybrid of majority and/or minority gates and complementary metal oxide semiconductor (CMOS) based inverters and/or buffers. The adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.

Multi-cycle reset mechanism for a chain of majority gates having non-linear polar material

Described herein is a memory bit-cell that results in lower leakage and higher sensing margin. In at least one embodiment, a memory bit-cell comprises a plurality of capacitors, wherein an individual capacitor is coupled to a node and an individual plate-line. In at least one embodiment, memory bit-cell comprises a first transistor coupled to the node. In at least one embodiment, memory bit-cell comprises a second transistor coupled in series with the first transistor, wherein the second transistor is coupled to a bit-line, wherein the first transistor or the second transistor is controllable by a word-line, and wherein the word-line is parallel to the individual plate-line.

Non-linear polar material based multi-capacitor high density bit-cell

An apparatus and configuring scheme where a capacitive input circuit can be programmed to perform different logic functions by adjusting the switching threshold of the capacitive input circuit. Digital inputs are received by respective capacitors on first terminals of those capacitors. The second terminals of the capacitors are connected to a summing node. A pull-up and pull-down device are coupled to the summing node. The pull-up and pull-down devices are controlled separately. During a reset phase, the pull-up and/or pull-down devices are turned on or off in a sequence, and inputs to the capacitors are set to condition the voltage on node n. As such, a threshold for the capacitive input circuit is set. After the reset phase, an evaluation phase follows. In the evaluation phase, the output of the capacitive input circuit is determined based on the inputs and the logic function configured during the reset phase.

Stacked non-planar capacitors based multi-function linear threshold gate with input based adaptive threshold

Growing community of inventors

Portland, OR, United States of America

Sasikanth Manipatruni