Infineon Technologies Ag

Sascha Siegler

Georg Georgakos

Thomas Baumann

Stefan Bergler

Roswitha Deppe

Gerhard Weber

In a method for designing integrated circuits comprising replacement logic components, a plurality of logic cells and a plurality of filler cells which fill interspaces between the logic cells are positioned on a chip area. In this case, some or all of the filler cells represent replacement logic components for the integrated circuit and have been or are interconnected or wired in such a way that they form capacitances in the integrated circuit.

Method for designing integrated circuits comprising replacement logic gates

A clock control cell for production of an output clock signal from an input clock signal has a hold element and an output stage. The hold element is preceded by a signal level converter, with the signal level converter designed such that it converts an input signal to an output signal at predetermined signal levels, wherein the input clock signal is the input signal of the signal level converter.

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Unterhaching, Germany

Sascha Siegler