International Business Machines Corporation

Globalfoundries Inc.

Sascha Junghans

Matthias Klein

Norbert Hagspiel

Joerg H Walter

Ekaterina M Ambroladze

Thomas Schlipf

Donald W Schmidt

Christoph Raisch

Peter Dana Driever

Marco Kraemer

Bernd Nerz

David F Craddock

Eric N Lais

Garrett M Drapala

Girish Gopala Kurup

Gary E Strait

Andreas Koenig

Christian Jacobi

Martin Recktenwald

Pak-kin Mak

Robert J Sonnelitter, Iii

Hans-Werner Tast

Christian Habermann

Chad G Wilson

Kevin Lopes

Jeorg Walter

Julian Heyne

Fahmiyah Samad

Ananth Garikapati

A data processing system includes a system fabric coupling a coherence manager and an input/output (I/O) requestor. The I/O requestor issues a first snoop request of a first I/O store operation and a subsequent second snoop request of a second I/O store operation. Each of the first and second snoop requests specifies an update to a respective storage location identified by a coherent memory address. The I/O requestor receives respective ownership coherence responses for each of the first and second I/O store operations. The respective first and second ownership coherence responses indicate the coherence manager has concurrent coherence ownership of the memory address for both the first and second I/O store operations. In response to receipt of each of the ownership coherence responses, the I/O requestor issues respective first and second execute coherence responses to command the coherence manager to initiate updates to the respective storage locations.

Input/output (I/O) store protocol for pipelining coherent operations

Combining PCIe partial store commands along cache line boundaries, including: receiving a plurality of Peripheral Component Interface express (PCIe) packets; splitting the plurality of PCIe packets along cache line boundaries to generate a plurality of partial store commands; and combining one or more sets of partial store commands to generate one or more combined partial store commands aligned to the cache line boundaries.

Combining peripheral component interface express partial store commands along cache line boundaries

An interrupt signal is provided to a guest operating system. A bus connected module is operationally connected with a plurality of processors via a bus attachment device. The bus attachment device receives an interrupt signal from the bus connected module with an interrupt target ID identifying one of the processors assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device checks whether the target processor is running using a running indicator provided by an interrupt table entry stored in a memory operationally connected with the bus attachment device. If the target processor is running, the bus attachment device forwards the interrupt signal to the target processor for handling. A translation of the interrupt target ID to a logical processor ID of the target processor is used to address the target processor directly.

Directed interrupt virtualization with running indicator

An interrupt signal is provided to a guest operating system. A bus attachment device receives an interrupt signal from a bus connected module with an interrupt target ID identifying a processor assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device checks whether the target processor is blocked from receiving interrupt signals using an interrupt blocking indicator provided by an interrupt table entry stored in a memory operationally connected with the bus attachment device. If the target processor unblocked, the bus attachment device forwards the interrupt signal to the target processor for handling. A translation of the interrupt target ID to a logical processor ID of the target processor is used to address the target processor directly.

Directed interrupt virtualization with blocking indicator

A data processing apparatus includes a number of processor cores, a shared processor cache, a bus unit and a bus controller. The shared processor cache is connected to each of the processor cores and to a main memory. The bus unit is connected to the shared processor cache by a bus controller for transferring data to/from an I/O device. In order to achieve further improvements to the data transfer rate between the processor cache and I/O devices, the bus controller is configured, in response to receiving a descriptor from a processor core, to perform a direct memory access to the shared processor cache for transferring data according to the descriptor from the shared processor cache to the I/O device via the bus unit.

Data transfer using a descriptor

Creating hash values based on bit values of an input vector. An apparatus includes a first and a second hash table, a first and second hash function generator adapted to configure a respective hash function for a creation of a first and second hash value based on the bit values of the input vector. The hash values are stored in the respective hash tables. An evaluation unit includes a comparison unit to compare a respective effectiveness of the first hash function and the second hash function, and an exchanging unit responsive to the comparison unit adapted to replace the first hash function by the second hash function.

Dynamic evaluation and adaption of hardware hash function

A method, computer program product, and system for maintaining a proper ordering of a data steam that includes two or more sequentially ordered stores, the data stream being moved to a destination memory device, the two or more sequentially ordered stores including at least a first store and a second store, wherein the first store is rejected by the destination memory device. A computer-implemented method includes sending the first store to the destination memory device. A conditional request is sent to the destination memory device for approval to send the second store to the destination memory device, the conditional request dependent upon successful completion of the first store. The second store is cancelled responsive to receiving a reject response corresponding to the first store.

Increased bandwidth of ordered stores in a non-uniform memory subsystem

A system and method to transfer an ordered partial store of data from a controller to a memory subsystem receives the ordered partial store of data into a buffer of the controller. The method also includes issuing a preinstall command to the memory subsystem, wherein the preinstall command indicates that data from a number of addresses of memory corresponding with a target memory location be obtained in local memory of the memory subsystem along with ownership of the data for subsequent use. A query command is issued to the memory subsystem. The query command requests an indication from the memory subsystem that the memory subsystem is ready to receive and correctly serialize the ordered partial store of data. The ordered partial store of data is transferred from the controller to the memory subsystem.

Preinstall of partial store cache lines

A method for coupling transactions with a configurable ordering controller in a computer system. The method comprises sending, by a coupling device, first data packets with an unordered attribute being set to an ordering controller. The method further comprises sending, by the coupling device, second data packets with requested ordering to the ordering controller, back-to-back after the first data packets, without waiting until all of the first data packets are completed. The method further comprises sending, by the ordering controller, the first data packets to a memory subsystem in a relaxed ordering mode, wherein the ordering controller sends the first data packets to the memory subsystem in an arbitrary order, and wherein the ordering controller sends the second data packets to the memory subsystem after sending all of the first data packets to the memory subsystem.

Configurable ordering controller for coupling transactions

A computer system with a configurable ordering controller for coupling transactions. The computer system comprises a coupling device configured to send first data packets with an unordered attribute being set to an ordering controller. The computer system further comprises the coupling device configured to send second data packets with requested ordering to the ordering controller, back-to-back after the first data packets, without waiting until all of the first data packets are completed. The computer system further comprises the ordering controller configured to send the first data packets to a memory subsystem in a relaxed ordering mode, wherein the ordering controller sends the first data packets to the memory subsystem in an arbitrary order, and wherein the ordering controller sends the second data packets to the memory subsystem after sending all of the first data packets to the memory subsystem.

Embodiments include a technique for management of data transactions, where the technique includes receiving, at a link interface, a packet from an I/O device, wherein the packet includes address information, and performing, by a host bridge, an address translation for the address information included in the packet. The technique also includes responsive to performing the address translation, determining a target page associated with a translated address of the packet is for at least one of a payload target page or a signaling target page, and appending a flag to a command based at least in part on the target page being associated with the translated address of the packet. The technique includes transmitting the command to an ordering controller for ordering the packet.

Management of data transaction from I/O devices

A data processing apparatus is provided, which includes: a plurality of processor cores; a shared processor cache, the shared processor cache being connected to each of the processor cores and to a main memory; a bus controller, the bus controller being connected to the shared processor cache and performing, in response to receiving a descriptor sent by one of the processor cores, a transfer of requested data indicated by the descriptor from the shared processor cache to an input/output (I/O) device; a bus unit, the bus unit being connected to the bus controller and transferring data to/from the I/O device; wherein the shared processor cache includes means for prefetching the requested data from the shared processor cache or main memory by performing a direct memory access in response to receiving a descriptor from the one of the processor cores.

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Ammerbuch, Germany

Sascha Junghans