International Business Machines Corporation

Sasa Tomic

Roman Alexander Pletka

Nikolas Ioannou

Timothy J Fisher

Aaron Daniel Fry

Nikolaos Papandreou

Charles John Camp

Charalampos Pozidis

Ioannis Koltsidas

Radu Ioan Stoica

Thomas P Parnell

Andrew Dale Walls

Lincoln T Simmons

Antonios Kornilios Kourtis

Cheng-Chung Song

Jason Szecheong Ma

Thomas Mittelholzer

Christopher M Dennett

Razik S Ahmed

Matthew R Orr

Gary A Tressler

Brent William Yardley

Thomas D Weigold

Thomas J Griffin

Kevin E Sallese

Zoltan Arnold Nagy

Niels Dominic Pardon

Matt Reuter

A method for intra-block recovery from memory page read failures of memory pages is provided. The method comprises providing a data storage device comprising a plurality of memory pages. Corresponding memory pages are physically organized as a plurality of blocks comprising each the corresponding pages, each memory page comprising a plurality of non-volatile memory cells. The method comprises grouping memory pages of a block into at least one window. Each window comprises a plurality of memory pages of the block. The method further comprises determining a window parity page for each window of the block for a recovery of page read failures of the memory pages of the block, and upon determining that a predefined number of memory pages of the window is written or not yet written, maintaining the determined window parity page as part of the related window of memory pages of the block or not.

Addressing page-correlated read issues using intra-block parity

A computer-implemented method, according to one embodiment, includes: maintaining a first subset of the plurality of blocks in a first pool, where the blocks maintained in the first pool are configured in SLC mode. A second subset of the plurality of blocks is maintained in a second pool, where the blocks maintained in the second pool are configured in multi-bit-per-cell mode. A current I/O rate for the memory is identified during runtime, and a determination is made as to whether the current I/O rate is outside a first range. In response to determining that the current I/O rate is not outside the first range, the blocks maintained in the first pool are used to satisfy incoming host writes. Moreover, in response to determining that the current I/O rate is outside the first range, the blocks maintained in the second pool are used to satisfy incoming host writes.

Workload based relief valve activation for hybrid controller architectures

The invention relates to a method for adjusting a performance of a computing system, the method comprising receiving by the computing system at least one command to execute a computational workload from a client, applying by the computing system an identification method identifying a first system resource of the system resources which limits an execution performance of the computational workload, performing a temporary adjustment of an allocation of the first system resource to the client and evaluating whether this improves an execution performance of the computational workload, and, if this is the case, offering to the client to permanently adjust the allocation of the first system resource to the client and adjusting the allocation of the first system resource to the client permanently in case of receiving a corresponding instruction from the client. The invention also relates to a computing system and a computer program product which implement the method.

Computing system performance adjustment via temporary and permanent resource allocations

A computer-implemented method, according to one approach, includes: determining a current read heat value of each logical page which corresponds to write requests that have accumulated in a destage buffer. Each of the write requests is assigned to a respective write queue based on the current read heat value of each logical page which corresponds to the write requests. Moreover, each of the write queues correspond to a different page stripe which includes physical pages, the physical pages included in each of the respective page stripes being of a same type. Other systems, methods, and computer program products are described in additional approaches.

Data placement in write cache architecture supporting read heat data separation

A computer-implemented method, according to one embodiment, is for calibrating read voltages for a block of memory. The computer-implemented method includes: determining a calibration read mode of the block, and using the calibration read mode to determine whether pages in the block should be read using full page read operations. In response to determining that the pages in the block should not be read using full page read operations, a current value of a partial page read indicator for the block is determined. The block is further calibrated by reading only a portion of each page in the block, where the current value of the partial page read indicator determines which portion of each respective page in the block is read. Moreover, the current value of the partial page read indicator is incremented.

Calibrating pages of memory using partial page read operations

A RAID controller periodically collects an indication of a current compression ratio achieved by each of a plurality of storage devices within the RAID. The RAID controller determines a placement of data and the parity information within at least one of the plurality of storage devices according to at least one of a plurality of factors associated with the current compression ratio. The RAID controller writes the data and the parity information to the at least one of the plurality of storage devices according to the determined placement.

Adaptive data and parity placement using compression ratios of storage devices

A computer-implemented method, according to one approach, is for calibrating read voltages associated with a block of memory having more than one word-line therein. The computer-implemented method includes: for each of the word-lines in the block: calculating an absolute shift value for a reference read voltage associated with the given word-line. A relative shift value is also determined for each of the remaining read voltages associated with the given word-line, and the relative shift values are determined with respect to the reference read voltage. Moreover, each of the read voltages associated with the given word-line are adjusted using the absolute shift value and each of the respective relative shift values.

Calculating corrective read voltage offsets in non-volatile random access memory

A computer-implemented method, according to one embodiment, includes: determining a current operating state of a block of memory. The block includes more than one type of page therein, and at least one read voltage is associated with each of the page types. The current operating state of the block is further used to produce a hybrid calibration scheme for the block which identifies a first subset of the read voltages, and a second subset of the read voltages. The read voltages in the second subset are further organized in one or more groupings. A unique read voltage offset value is calculated for each of the read voltages in the first subset, and a common read voltage offset value is also calculated for each grouping of read voltages in the second subset.

Hybrid read voltage calibration in non-volatile random access memory

A memory controller for recovering data due to transient effects of nonvolatile memory is provided. A memory controller receives a read request for a page stored in the nonvolatile memory. The memory controller issues a first read command. The memory controller records a time stamp for the first read command. In response to a failure during the first read command, the memory controller waits for a delay after the recorded time stamp and the memory controller issues a second read command to the page, wherein the second read command applies a read voltage offset that is dependent on the delay between the first read command and the second read command and at least one other parameter.

Data recovery due to transient effects in NAND flash memories

Aspects of the present invention disclose a method, computer program product, and system for controlling operation of an array of non-volatile memory cells comprising cells which are selectively configurable for single-bit and multibit storage. The method includes a memory controller selectively configuring the array for operation in a hybrid mode, in which the array comprises both cells configured for single-bit storage and cells configured for multibit storage, and a multibit mode in which all cells in the array are configured for multibit storage. The method further includes the memory controller dynamically switching between the hybrid and multibit mode configurations of the array corresponding to array capacity-usage traversing a defined threshold level associated with enhance endurance of the array.

Memory controllers for solid-state storage devices

A computer-implemented method, according to one embodiment, includes: determining whether a number of blocks included in a first ready-to-use (RTU) queue is in a first range of the first RTU queue. In response to determining that the number of blocks included in the first RTU queue is in the first range, a determination is made as to whether a number of blocks included in a second RTU queue is in a second range of the second RTU queue. Moreover, in response to determining that the number of blocks included in the second RTU queue is not in the second range, valid data is relocated from one of the blocks in a first pool which corresponds to the first RTU queue. The block in the first pool is erased, and transferred from the first pool to the second RTU queue which corresponds to a second pool.

Adapting memory block pool sizes using hybrid controllers

An apparatus, according to one embodiment, includes non-volatile memory configured to store data, and a controller and logic integrated with and/or executable by the controller, the logic being configured to: determine, by the controller, that at least one block of the non-volatile memory and/or portion of a block of the non-volatile memory meets a retirement condition, re-evaluate, by the controller, the at least one block and/or the portion of a block to determine whether to retire the at least one block and/or the portion of a block, indicate, by the controller, that the at least one block and/or the portion of a block remains usable when a result of the re-evaluation is not to retire the block, and indicate, by the controller, that the at least one block and/or the portion of a block is retired when the result of the re-evaluation is to retire the block.

Endurance enhancement scheme using memory re-evaluation

A computer-implemented method, according to one embodiment, is for wear leveling blocks of memory. The computer-implemented method includes: determining the health of blocks of memory which are configured in multi-bit-per-cell mode. The blocks configured in multi-bit-per-cell mode are in a second pool, while blocks that are configured in single-level cell (SLC) mode are in a first pool. Moreover, the computer-implemented method is performed in some approaches with a proviso that the health of a block of memory is not determined while the block is configured in SLC mode. Moreover, health values are assigned to the blocks of memory in the second pool based on the health of the respective block. Each of the health values is further correlated with a respective data temperature.

Managing blocks of memory based on block health using hybrid controllers

Performing a calibration of a NAND flash memory block that is in an open state. An open state of the NAND flash memory block is detected, the NAND flash memory block comprising a plurality of memory pages, each of which comprising a plurality of memory cells. A group of pages of the NAND flash memory block being in an open state having comparable characteristics is identified. A calibration of read voltage values to pages of the group of identified pages is performed.

Calibration of open blocks in NAND flash memory

A computer-implemented method, according to one embodiment, is for maintaining heat information of data while in a cache. The computer-implemented method includes: transferring data from non-volatile memory to the cache, such that the data is stored in a first page in the cache. Previous read and/or write heat information associated with the data is maintained by preserving one or more bits in a hash table which correspond to the data in the first page. Moreover, the data is destaged from the first page in the cache to the non-volatile memory, and the one or more bits in the hash table which correspond to the data are updated to reflect current read and/or write heat information associated with the data.

Growing community of inventors

Kilchberg, Switzerland

Sasa Tomic