Intel Corporation

Sarvesh H Kulkarni

Kevin X Zhang

Zhanping Chen

Uddalak Bhattacharya

Vincent E Dorgan

Yu-Lin Chao

Walid M Hafez

Zhiyong Ma

Xianghong Tong

Kevin D Johnson

Matthew B Pedersen

Ram K Krishnamurthy

Sanu K Mathew

Mark A Anders

Jeffrey Hicks

Inanc Meric

Venkata Krishna Rao Vangara

Embodiments herein may describe techniques for an integrated circuit including a MOSFET having a source area, a channel area, a gate electrode, and a drain area. The channel area may include a first channel region with a dopant of a first concentration next to the source area, and a second channel region with the dopant of a second concentration higher than the first concentration next to the drain area. A source electrode may be in contact with the source area, a gate oxide layer above the channel area, and the gate electrode above the gate oxide layer. A first resistance exists between the source electrode and the gate electrode. A second resistance exists between the source electrode, the gate electrode, and a path through the gate oxide layer to couple the source electrode and the gate electrode after a programming operation is performed. Other embodiments may be described and/or claimed.

Metal-oxide-semiconductor field-effect-transistors (MOSFET) as antifuse elements

Memory cell circuitry is disclosed. The memory cell circuitry includes a first transistor configured to have a threshold voltage of the first transistor modulated by hot carrier injection, a second transistor coupled to the first transistor and configured to have a threshold voltage of the second transistor modulated by hot carrier injection, a word line coupled to a gate of the first transistor and to a gate of the second transistor, a first bit line coupled to the first transistor and a second bit line coupled to the second transistor. In addition, the memory cell circuitry includes a source line coupled to the drain of the first transistor and to the drain of the second transistor, the word line and the source line configured to cause hot carrier injection (HCI) into the first transistor when a first supply voltage is applied to the word line and the source line, and the second bit line is floated and the first bit line is grounded. The word line and the source line are configured to cause hot carrier injection into the second transistor when the first supply voltage is applied to the word line and the source line, and the first bit line is floated and the second bit line is grounded. Methods utilizing this technology for generating a multi-time programmable non-volatile memory and a random number generator for physical unclonable function applications are included in this disclosure.

Hot carrier injection fuse memory

Embodiments herein may describe techniques for an integrated circuit including a MOSFET having a semiconductor well, a source area and a drain area next to the semiconductor well, a gate electrode, and a base terminal. The gate electrode may be coupled to the base terminal, hence forming a floating body MOSFET. A junction may exist between the drain area and the semiconductor well. A first resistance may exist between the source area and the drain area through the semiconductor well. A programming operation may be performed when the gate electrode is coupled to a high impedance, a programming voltage is applied at the source area, and the drain area is coupled to a ground voltage to break the junction between the drain area and the semiconductor well to generate a current between the source area, the semiconductor well, and the drain area. Other embodiments may be described and/or claimed.

Floating body metal-oxide-semiconductor field-effect-transistors (MOSFET) as antifuse elements

Methods of forming and using a microelectronic structure are described. Embodiments include forming a diode between a metal fuse gate and a PMOS device, wherein the diode is disposed between a contact of the metal fuse gate and a contact of the PMOS device, and wherein the diode couples the contact of the metal fuse gate to the contact of the PMOS device.

Methods of forming secured metal gate antifuse structures

A memory cell includes a fuse and at least one transistor. The transistor is used to control the programming or sensing of the fuse. A program voltage is applied to a stack of first and second conductive layers. A first portion of the stack couples the program voltage to a terminal of the transistor in a cell. A second portion of the stack couples the program voltage to a terminal of the transistor in another cell.

Programmable read only memory

Techniques and circuitry are disclosed for efficiently implementing programmable memory array circuit architectures, such as PROM, OTPROM, and other such programmable non-volatile memories. The circuitry employs an antifuse scheme that includes an array of memory bitcells, each containing a program device and an antifuse element configured with current path isolation well and for storing the memory cell state. The bitcell configuration, which can be used in conjunction with column/row select circuitry, power selector circuitry, and/or readout circuitry, allows for high-density memory array circuit designs and layouts.

Antifuse programmable memory array

A method and apparatus for an address generation circuit. In one embodiment, the method includes computing a carry-in for at least one group of a predetermined number of bits of a propagate and a generate signal formed from a plurality of logical address components. Once the carry-in is computed, a plurality of conditional sums are generated for a logiccarry-in and a logiccarry-in. Subsequently, a sum is selected from the plurality of conditional sums to form a first portion of an effective address from the logical address components in a first stage and a second portion of the effective address in a second stage. In one embodiment, a fully dynamic high-performance sparse tree adder circuit that generates one in four carries, is used to form an address generation circuit, in accordance with one embodiment. Other embodiments are described and claimed.

Growing community of inventors

Hillsboro, OR, United States of America

Sarvesh H Kulkarni