International Business Machines Corporation

Globalfoundries Inc.

Sarunya Bangsaruntip

Jeffrey W Sleight

Guy M Cohen

Amlan Majumdar

Josephine B Chang

Isaac Lauer

Shreesh Narasimha

Shu-Jen Han

Ying Di Zhang

Leland Chang

Sebastian Ulrich Engelmann

Ali Afzali-Ardakani

Conal Eugene Murray

Steven John Koester

Michael A Guillorn

Katherine Lynn Saenger

Chung-Hsun Lin

Nicholas C M Fuller

Hsinyu Tsai

Michael Engel

Lidija Sekaric

Qingyun Yang

Jeffrey W Sleights

Chung H Lam

Daniel C Edelstein

Andres Bryant

Alejandro Gabriel Schrott

Baleegh Abdo

Matthew Joseph Breitwisch

Eric Andrew Joseph

Patryk Gumann

David Lee Rath

Salvatore Bernardo Olivadese

Bipin Rajendran

Ho-Cheol Kim

Heike E Riel

Heinz Schmid

Sean Hart

Nicholas Torleiv Bronn

Mary Beth Rothwell

Siyuranga O Koswatta

William Dinan Hinsberg

George Gabriel Totir

Daniela Florentina Bogorin

Mikael T Bjoerk

Paul M Soloman

Stephen J Koester

Techniques for designing and fabricating quantum circuitry, including a coplanar waveguide (CPW), for quantum applications are presented. With regard to a CPW, a central conductor and two return conductor lines can be formed on a dielectric substrate, with one return conductor line on each side of the central conductor and separated from it by a space. The central conductor can have bridge portions that can be raised a desired distance above the substrate and base conductor portions situated between the bridge portions and in contact with the surface of the substrate; and/or portions of the substrate underneath the bridge portions of the central conductor can be removed such that the bridge portions, whether raised or unraised, can be the desired distance above the surface of the remaining substrate, and the base conductor portions can be in contact with other portions of the surface of the substrate that were not removed.

Low loss conductive line using bridged conductor

Techniques regarding methods and/or apparatuses for protecting metal substrates during one or more lithography processes are provided. For example, one or more embodiments described herein can comprise a method that can include coating a metal substrate with a polymer film that self-assembles on a metal oxide positioned on a surface of the metal substrate. The method can also include covalently bonding the polymer film to the metal oxide.

Metal surface protection

Techniques for trapping quasiparticles in superconductor devices are provided. A superconductor device can comprise a substrate layer. The superconductor device can further comprise a first superconductor layer composed of a first superconductor material, on a first surface of a substrate layer. The superconductor device can further comprise a trapping material buried in the first superconductor layer, wherein the trapping material is formulated to trap quasiparticles.

Superconductor devices having buried quasiparticle traps

A field effect transistor including a dielectric layer on a substrate, a nano-structure material (NSM) layer on the dielectric layer, a source electrode and a drain electrode formed on the NSM layer, a gate dielectric formed on at least a portion of the NSM layer between the source electrode and the drain electrode, a T-shaped gate electrode formed between the source electrode and the drain electrode, where the NSM layer forms a channel of the FET, and a doping layer on the NSM layer extending at least from the sidewall of the source electrode to a first sidewall of the gate dielectric, and from a sidewall of the drain electrode to a second sidewall of the gate dielectric.

Fabrication of nanomaterial T-gate transistors with charge transfer doping layer

In one aspect, a method for placing carbon nanotubes on a dielectric includes: using DSA of a block copolymer to create a pattern in the placement guide layer on the dielectric which includes multiple trenches in the placement guide layer, wherein there is a first charge on sidewall and top surfaces of the trenches and a second charge on bottom surfaces of the trenches, and wherein the first charge is different from the second charge; and depositing a carbon nanotube solution onto the dielectric, wherein self-assembly of the deposited carbon nanotubes within the trenches occurs based on i) attractive forces between the first charge on the surfaces of the carbon nanotubes and the second charge on the bottom surfaces of the trenches and ii) repulsive forces between the first charge on the surfaces of the carbon nanotubes and the first charge on sidewall and top surfaces of the trenches.

Placement of carbon nanotube guided by DSA patterning

A method of modifying a wafer having a semiconductor disposed on an insulator is provided and includes forming pairs of semiconductor pads connected via respective nanowire channels at each of first and second regions with different initial semiconductor thicknesses and reshaping the nanowire channels into nanowires to each have a respective differing thickness reflective of the different initial semiconductor thicknesses.

Generation of multiple diameter nanowire field effect transistors

Non-planar semiconductor devices including at least one semiconductor nanowire having a tapered profile which widens from the source side of the device towards the drain side of the device are provided which have reduced gate to drain coupling and therefore reduced gate induced drain tunneling currents.

Tapered nanowire structure with reduced off current

A floating gate transistor, memory cell, and method of fabricating a device. The floating gate transistor includes one or more gated wires substantially cylindrical in form. The floating gate transistor includes a first gate dielectric layer at least partially covering the gated wires. The floating gate transistor further includes a plurality of gate crystals discontinuously arranged upon the first gate dielectric layer. The floating gate transistor also includes a second gate dielectric layer covering the plurality of gate crystals and the first gate dielectric layer.

Nanowire floating gate transistor

Techniques for defining a damascene gate in nanowire FET devices are provided. In one aspect, a method of fabricating a FET device is provided including the following steps. A SOI wafer is provided having a SOI layer over a BOX. Nanowires and pads are patterned in the SOI layer in a ladder-like configuration. The BOX is recessed under the nanowires. A patternable dielectric dummy gate(s) is formed over the recessed BOX and surrounding a portion of each of the nanowires. A CMP stop layer is deposited over the dummy gate(s) and the source and drain regions. A dielectric film is deposited over the CMP stop layer. The dielectric film is planarized using CMP to expose the dummy gate(s). The dummy gate(s) is at least partially removed so as to release the nanowires in a channel region. The dummy gate(s) is replaced with a gate conductor material.

Process for forming a surrounding gate for a nanowire using a sacrificial patternable dielectric

An integrated circuit includes a plurality of gate-all-around (GAA) nanowire field effect transistors (FETs), a plurality of omega-gate nanowire FETs, and a plurality of planar channel FETs, wherein the plurality of GAA FETs, the plurality of omega-gate nanowire FETs, and the plurality of planar channel FETs are disposed on a single wafer.

Planar and nanowire field effect transistors

A nanowire tunnel device includes a nanowire suspended above a semiconductor substrate by a first pad region and a second pad region, the nanowire having a channel portion surrounded by a gate structure disposed circumferentially around the nanowire, an n-type doped region including a first portion of the nanowire adjacent to the channel portion, and a p-type doped region including a second portion of the nanowire adjacent to the channel portion.

Nanowire PIN tunnel field effect devices

A method of fabricating an electronic device includes the following steps. At least one first set and at least one second set of nanowires and pads are etched in an SOI layer of an SOI wafer. A first gate stack is formed that surrounds at least a portion of each of the first set of nanowires that serves as a channel region of a capacitor device. A second gate stack is formed that surrounds at least a portion of each of the second set of nanowires that serves as a channel region of a FET device. Source and drain regions of the FET device are selectively doped. A first silicide is formed on the source and drain regions of the capacitor device that extends at least to an edge of the first gate stack. A second silicide is formed on the source and drain regions of the FET device.

Nanowire capacitor for bidirectional operation

Growing community of inventors

Mount Kisco, NY, United States of America

Sarunya Bangsaruntip