Texas Instruments Corporation

Sarma S Gunturi

Mark A Dexter

Cetin Kaya

Freidoon Mehrad

Bruce E Flinchbaugh

Aditya Srivastava

Thomas Warren Lassiter

Catherine M Huber

Kyle A Picone

Paul A Chintapalli

Steven B Dolins

Robert L Love

Michelle A Boyer

An integrated circuit containing a memory array with memory bits and a differential sense amplifier for reading the logic state of the memory bits. The integrated circuit also contains redundant vias which are in the via path that couples a bitline to Vss. Moreover, an integrated circuit containing a FLASH memory bit with redundant vias in the via path from the bitline to Vss.

Memory bit redundant vias

A method for fabricating a flash memory device having a self-aligned source includes providing a semiconductor substrate having a source region separated from a drain region by a channel region. The method also includes forming an isolation structure in the semiconductor substrate that crosses the source, drain, and channel regions of the semiconductor substrate. The method also includes forming a continuous stack structure outwardly from the channel region of the semiconductor substrate and the isolation structure. The method includes depositing a bottom anti-reflective layer over the semiconductor substrate, the isolation structure and the stack structure to substantially uniformly planarize the semiconductor substrate and the isolation structure. The method further includes depositing a photoresist layer over select portions of the bottom anti-reflective layer and the continuous stack structure to form a self-aligned source pattern using a photo mask. The method includes etching the isolation structure and the bottom anti-reflective layer corresponding to the self aligned source pattern using a low selectivity etch process to remove a portion of the isolation structure and etching a remaining portion of the isolation structure using high selectivity etch process.

Method for fabricating a self-aligned source line flash memory device

A method of fabricating a semiconductor device which includes providing a silicon substrate having a patterned mask thereover to expose a portion of the surface of the substrate. The exposed surface portion is oxidized to form a sacrificial silicon oxide region to a predetermined depth in the substrate at the exposed portions of the substrate. The sacrificial silicon oxide is then removed by a HF etch and a second region of silicon oxide is formed in the substrate in the region from which the sacrificial silicon oxide was removed. The step of removing the silicon oxide also includes removing a portion of the pad oxide. The sacrificial silicon oxide has a thickness less than the second region of silicon oxide which is from about 10 percent to about 30 percent of the thickness of the second region of silicon oxide. The oxidation steps are thermal oxidation steps in an oxygen-containing ambient.

Planarization of LOCOS through recessed reoxidation techniques

A method of fabricating a semiconductor device having a memory array (9) that includes a source line (24) is provided. The method of forming the source line (24) may include providing a semiconductor substrate (52) having a source region (60) separated from a drain region (62) by a channel region (64). An isolation structure (70) may be formed in the semiconductor substrate (52). The isolation structure (70) may cross the source region (60), the drain region (62), and the channel region (64) of the semiconductor substrate (52). An isolation dielectric material (78) may be formed within the isolation structure (70). A continuous stack structure (50) may be formed outwardly from the channel region (64) of the semiconductor substrate (52) and the isolation structure (70). A first photomask (100) may be formed outwardly from the continuous stack structure (50) and the semiconductor substrate (52). The first photomask (100) may expose a strip region (102) of the semiconductor substrate (52) and the isolation structure (70). The isolation dielectric material (78) may be removed from the exposed portion the isolation structure (70) to expose the semiconductor substrate (52). A dopant may be implanted into the exposed semiconductor substrate (52) to form the source line (24) in the semiconductor device.

Source line fabrication process for flash memory

An improved apparatus and process for detecting aberrations in production process operations is provided. In one embodiment, operations of a plasma etch reactor (10) are monitored to detect aberrations in etching operations. A reference end-point trace (EPT) is defined (62) for the etch process. Regions are defined in the reference end-point trace (70) and characteristics and tolerances for each region are defined (72-80). The etcher is run and an actual EPT is obtained (82) from the running of the etcher. The actual EPT is analyzed to identify proposed regions of the actual EPT (86), and then the proposed regions of the actual EPT are matched with regions of the reference EPT (96). The system employs a series of heuristic functions in matching proposed regions of the actual EPT with regions of the reference EPT. Characteristics of the matched regions of the actual end-point trace are compared (66) with characteristics of the corresponding regions of the reference end-point trace to determine whether aberrations have occurred during the etch process. The invention provides for an improved matching and improved comparison of actual end-point traces with reference end-point traces.

Growing community of inventors

Plano, TX, United States of America

Sarma S Gunturi