Intel Corporation

Intel IP Corporation

Sarit Zur

Igal Kushnir

Ofir Degani

Rotem Banin

Gil Horovitz

Assaf Ben-Bassat

Eshel Gordon

Ronen Kronfeld

Ofer Benjamin

Ehud Reshef

Stefano Pellerano

Brent R Carlton

Sebastian Sievert

Avi Sulimarski

Mustafijur Rahman

Lior Shakedd

Sergey Bershansky

Eli Borokhovich

Oren Ezra Avrham

Oren Ezra Avraham

A transceiver may include a transmit path and a receive path that are each coupled to a radio frequency (RF) interface, and a self-interference canceller (SIC). The SIC is coupled between the transmit and the receive paths. The SIC is configured to cancel a self-interference signal from a received signal on the receive path based on a transmit signal on the transmit path.

Self-interference canceller

An apparatus for regulating a supply voltage supplied from a voltage source to a load via a supply line is provided. The apparatus includes a control circuit configured to generate a control signal based on a difference between a value of the supply voltage and a nominal value of the supply voltage. Further, the apparatus includes a switch circuit configured to couple a charged capacitive element to the supply line based on the control signal.

Apparatus and method for regulating a supply voltage

A frequency estimator for estimating a frequency, including a counter configured to count an integer number of full clock cycles during a measurement time window; a Time-to-Digital Converter (TDC) configured to measure a fraction of a clock cycle during the measurement time window; and a processor configured to determine the estimated frequency based on the counted number of full clock cycles and the measured fraction of the clock cycle.

Frequency estimation

A phase interpolator is provided. The phase interpolator includes a plurality of first interpolation cells each configured to supply a first current to a common node of the phase interpolator. Further, the phase interpolator includes a plurality of second interpolation cells each configured to supply a second current to the common node. The second current is lower than the first current, wherein a sum of the plurality of second currents supplied to the common node by the plurality of second interpolation cells is substantially equal to the first current.

Phase interpolator, apparatus for phase interpolation, digital-to-time converter, and methods for phase interpolation

Systems, apparatuses, methods, and computer-readable media, are provided for Radio Frequency (RF) gain calibration and/or characterization of one or more RF transmitter and/or receivers, to calibrate RF gain variations caused by various factors, such as temperature changes, operating frequency changes, processing and manufacturing variations, and/or offset of voltage supplies and controls. RF gain calibration and/or characterization are performed with respect to active RF components. Other embodiments may be described and/or claimed.

Technologies for online gain lineup in millimeter wave transceivers

Systems, methods, and circuitries are disclosed for generating a desired signal from a received signal. In one example a signal cancellation system includes local oscillator (LO) downconverter circuitry, frequency offset (FO) signal estimation circuitry, and cancellation circuitry. The LO downconverter is configured to downconvert the received signal using an LO signal having an LO frequency to generate a downconverted received signal. The FO signal estimation circuitry includes FOLO generation circuitry configured to modify the LO signal to generate a FOLO signal having an offset frequency that is different from the LO frequency and FOLO downconverter circuitry configured to use the FOLO signal to downconvert a signal derived from the received signal to generate a downconverted FO signal. The cancellation circuitry is configured to cancel either the downconverted received signal or the downconverted FO signal from the received signal to generate the desired signal.

Signal cancellation system and method

Embodiments of a reference path circuit and communication device are generally described herein. The reference path circuit may include an injection locked multiplier (ILM) and a group of one or more buffer amplifiers. The ILM may receive a sinusoidal reference signal from a reference oscillator at a reference frequency. The ILM may generate a sinusoidal ILM output signal at an ILM output frequency that is based on an integer multiple of the reference frequency. The integer multiple of the reference frequency may be within a locking range of the ILM that may be based on a resonant frequency of the ILM. The group of one or more buffer amplifiers may generate an output clock signal for input to the frequency synthesizer. The output clock signal may be based on a sign function of the ILM output signal.

Reference signal path for clock generation with an injection locked multiplier (ILM)

An apparatus for a low-power radar detection (LPRD) receiver is proposed in this disclosure. The LPRD receiver comprises an analog-to-digital converter (ADC) circuit configured to receive an analog dynamic frequency selection (DFS) signal associated with a DFS channel in a DFS frequency band to generate a digital DFS signal. The ADC circuit comprises a finite impulse response (FIR) filter circuit configured to sample the analog DFS signal at an FIR sampling rate determined based on a predetermined frequency plan associated with the DFS frequency band to generate a sampled DFS signal; and an ADC conversion circuit configured to convert the sampled DFS signal to the digital DFS signal at an ADC conversion rate that is lower than the FIR sampling rate.

Unique frequency plan and baseband design for low power radar detection module

Control circuitry for use in generating a local oscillator (LO) signal is provided. Synthesizer control circuitry is configured to control synthesizer circuity to generate an analog oscillator signal having a first frequency at which phase noise is minimized. DS control circuitry is configured to generate a control word or message to cause DS circuitry to generate a digital DS signal having a desired frequency when the DS circuitry is clocked by the oscillator signal having the first frequency. The desired frequency is proportional to the LO signal frequency. The digital DS signal generated by the DS circuitry is used to generate the LO signal. Thus the first frequency used to clock the DS circuitry is selected to optimize the oscillator rather than having some relationship to the LO frequency. In addition, a single synthesizer may be used in order to simultaneously generate many LO signals.

Local oscillator signal generation using opportunistic synthesizer to clock digital synthesis

Described herein are technologies related to an implementation of a time interleaved digital-to-time converter (DTC) topology to generate high frequency phase modulated local oscillator (LO) signals. A first and second DTC are connected to an oscillator where outputs of the two DTCs are combined to generate a phase modulated signal and the two DTCs have a frequency rate that is half the frequency rate of the phase modulated signal. The two DTCs can operate at a 50 percent or lower duty cycle.

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Petah-Tikva, Israel

Sarit Zur