Applied Materials, Inc.

Saravjeet Singh

Ajay Kumar

Wei-Sheng Lei

Brad Eaton

Madhava Rao Yalamanchili

James Matthew Holden

Dmitry Lubomirsky

Kenneth David Schatz

Roy C Nangoy

Tien Fak Tan

Alan Tso

Todd J Egan

Aparna Iyer

Tae Won Kim

Soonam Park

Jingchun Zhang

Amitabh Sabharwal

Dimitri R Kioussis

Jivko Dinev

Marlin Wijekoon

LokKee Loh

Manoocher Birang

Banqiu Wu

Zihui Li

Tong Liu

Tae Seung Cho

Nicolay Kovarsky

Hanshen Zhang

Laksheswar Kalita

Jon Christian Farr

Sharma V Pamarthy

Aron Rosenfeld

Graeme Jamieson Scott

Lok Kee Loh

Sheshraj L Tulshibagwale

Tae Wan Kim

Michael Xiaoxuan Yang

Yezdi N Dordi

Hooman Hafezi

Peter K Loewenhardt

Suketu Arun Parikh

Seshadri Ramaswami

Khiem K Nguyen

Joseph Frederick Behnke

Alexander Tam

Rohit Mishra

John M Yamartino

Puneet Bajaj

Khalid Mohiuddin Sirajuddin

Chirantha P Rodrigo

Satya Gowthami Achanta

Sonal A Srivastava

Tsz Keung Cheung

Deepak Doddabelavangala Srikantaiah

The present technology includes improved gas distribution designs for forming uniform plasmas during semiconductor processing operations or for treating the interior of semiconductor processing chambers. While conventional gas distribution assemblies may receive a specific reactant or reactant ratio which is then distributed into the plasma region, the presently described technology allows for improved control of the reactant input distribution. The technology allows for separate flows of reactants to different regions of the plasma to offset any irregularities observed in process uniformity. A first precursor may be delivered to the center of the plasma above the center of the substrate/pedestal while a second precursor may be delivered to an outer portion of the plasma above an outer portion of the substrate/pedestal. In so doing, a substrate residing on the pedestal may experience a more uniform etch or deposition profile across the entire surface.

Multi-zone gas distribution systems and methods

Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

Wafer dicing using femtosecond-based laser and plasma etch

An apparatus for distributing plasma products includes first and second electrodes that each include planar surfaces. The first electrode forms first apertures from a first planar surface to a second planar surface; the second electrode forms second apertures from the third planar surface to the fourth planar surface. The electrodes couple through one or more adjustable couplers such that the third planar surface is disposed adjacent to the second planar surface with a gap therebetween, the gap having a gap distance. Each of the adjustable couplers has a range of adjustment. The first and second apertures are arranged such that for at least one position within the ranges of adjustment, none of the first apertures aligns with any of the second apertures to form an open straight-line path extending through both the first and second electrodes.

Two piece electrode assembly with gap for plasma control

Exemplary semiconductor processing chamber showerheads may include a dielectric plate characterized by a first surface and a second surface opposite the first surface. The dielectric plate may define a plurality of apertures through the dielectric plate. The dielectric plate may define a first annular channel in the first surface of the dielectric plate, and the first annular channel may extend about the plurality of apertures. The dielectric plate may define a second annular channel in the first surface of the dielectric plate. The second annular channel may be formed radially outward from the first annular channel. The showerheads may also include a conductive material embedded within the dielectric plate and extending about the plurality of apertures without being exposed by the apertures. The conductive material may be exposed at the second annular channel.

Ceramic showerheads with conductive electrodes

A semiconductor processing chamber may include a remote plasma region, and a processing region fluidly coupled with the remote plasma region. The processing region may be configured to house a substrate on a support pedestal. The support pedestal may include a first material at an interior region of the pedestal. The support pedestal may also include an annular member coupled with a distal portion of the pedestal or at an exterior region of the pedestal. The annular member may include a second material different from the first material.

Methods and systems to enhance process uniformity

Exemplary etching methods may include flowing a hydrogen-containing precursor into a semiconductor processing chamber. The methods may include flowing a fluorine-containing precursor into a remote plasma region of the semiconductor processing chamber. The methods may include forming a plasma of the fluorine-containing precursor in the remote plasma region. The methods may include etching a pre-determined amount of a silicon-containing material from a substrate in a processing region of the semiconductor processing chamber. The methods may include measuring a radical density within the remote plasma region during the etching. The methods may also include halting the flow of the hydrogen-containing precursor into the semiconductor processing chamber when the radical density measured over time correlates to a produced amount of etchant to remove the pre-determined amount of the silicon-containing material.

Systems and methods for improved performance in semiconductor processing

Embodiments of the disclosure relate to a multi-plate faceplate having a first plate and a second plate. The first plate has a plurality of first plate openings. The second plate has a first surface, an opposed second surface and a plurality of second plate openings extending therethrough. The first surface is mechanically coupled to the first plate. A second plate opening has a conical portion configured to be fluidly coupled to a first plate opening and decreasing in cross-section in the depth direction thereof from the second surface. A surface of the conical portion is coated with a protective coating adjacent to the first and second surfaces. In another embodiment, the first plate has a protrusion extending therefrom into a recess formed inwardly of the first surface. The protrusion has a passage extending therethrough fluidly connected to the recess, which is fluidly connected to the second plate opening.

Multi-plate faceplate for a processing chamber

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Santa Clara, CA, United States of America

Saravjeet Singh