Cypress Semiconductor Corporation

Saravanan Murugesan

Arun Khamesra

Hariom Rai

Pulkit Shah

Karri Rajesh

Paul M Walsh

Kaveh Hosseini

Pragyan S Biswal

Gerard Baldwin

A primary-side-controlled fly-back converter is provided to eliminate cross-conduction between a power-switch (PS) on a primary side and a synchronous-rectifier (SR) on a secondary side when operating in continuous conduction mode (CCM). Generally, the converter includes a transformer having a primary coupled to a rectified AC input through the PS, and a secondary coupled to a DC output through the SR, the SR having a drain coupled to the secondary winding. A fly-back-controller includes a primary-controller operable to control a duty cycle of the PS, and a secondary-controller operable to turn OFF the SR when the PS turns ON in CCM. The secondary-controller includes a CCM zero-crossing-detector comparator having a first input coupled to the drain of the SR through a capacitor, and is operable to detect a sharp change in a drain voltage when the PS turns ON during CCM, and to output a signal to turn OFF the SR.

Synchronous rectifier scheme for continuous conduction mode in primary side controlled fly-back converter

An AC-DC converter with synchronous rectifier (SR) architecture and method for operating the same are described. Generally, a secondary side integrated circuit (IC controller of the AC-DC converter includes a peak-detector block coupled to detect peak voltages sensed on a SR-SNS pin. The peak-detector block comprises a peak comparator, a sample-and-hold (S/H) circuit, and a DC offset circuit. The peak comparator is coupled to receive a sinusoidal input from the SR-SNS pin. The S/H circuit is coupled to sample the sinusoidal input and to provide a peak sampled voltage. The DC offset voltage circuit is coupled between the output of the S/H circuit and a reference voltage input of the peak comparator to subtract a DC offset voltage from the peak sampled voltage.

Accurate peak detection architecture for secondary controlled AC-DC converter

An AC-DC converter with secondary side controller and synchronous rectifier (SR) architecture and method for operating the same are provided. Generally, the controller is implemented as an integrated circuit including a peak-detector module having a peak comparator with a first input coupled to a drain of the SR through a single SR sense (SR-SNS) pin to receive a sinusoidal input. A sample and hold (S/H) circuit with an input coupled to the SR-SNS pin samples the sinusoidal input and holds on an output of thereof a peak sampled voltage received on the input. A direct current (DC) offset voltage coupled between the output of the S/H circuit and the second input of the peak comparator subtracts an DC offset voltage from the peak sampled voltage to compensate for DC offset inaccuracies introduced by the S/H circuit and the peak comparator. Other embodiments are also disclosed.

Embodiments of a capacitance sensing system including an integrating amplifier and methods for operating the same to provide a higher slew rate and bandwidth are described. In one embodiment, the integrating amplifier comprises an input stage including an inverting input coupled to an electrode of a capacitor to sense a capacitance and a non-inverting input coupled to a reference potential, and an output stage including a compensating capacitor coupled to an output. The compensating capacitor comprises two smaller capacitors coupled in parallel and a switching element configured to open when the integrating amplifier is operated in a RESET mode decoupling one of the two smaller capacitors from the output to decrease capacitance of the compensating capacitor.

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Bengaluru, India

Saravanan Murugesan