Texas Instruments Corporation

Saravana Kumar Ganeshan

Anand Kannan

Bijoy Bhukania

Debapriya Sahu

Srinivasan Venkatraman

An electronic circuit separates frequency-overlapped GLONASS and GPS overlapped in an approximately 4 MHz passband. The circuit uses a multiple-path analog-to-digital converter circuit (ADC). A sampling rate circuit is coupled to concurrently operate the analog-to-digital converter circuit at a sampling rate between about 60 Msps and about 80 Msps. A digital processing circuit includes storage defining complex de-rotation and low pass filtering. The digital processing circuit is fed by the analog-to-digital converter circuit and is operable A) to establish an access rate and respective distinct phase increments for the complex de-rotation, B) to execute the complex de-rotation by combinations of trigonometric multiplications using the distinct phase increments approximately concurrently and C) to execute the low pass filtering on the complex de-rotation resulting at the access rate and respective distinct phase increments, thus delivering GPS and Glonass signals separated from each other.

Glonass/GPS de-rotation and filtering with ADC sampling at 60-80 MSPS

A wireless receiver for multiple frequency bands reception includes a single receive radio frequency (RF) circuit () having an RF bandpass substantially confined to encompass at least two non-overlapped such frequency bands at RF, a single in-phase and quadrature (approximately I, Q) pair of intermediate frequency (IF) sections (I,Q) having an IF passband, and a mixer circuit () including an in-phase and quadrature (I,Q) pair of mixers (I,Q) fed by said RF circuit () and having a local oscillator () with in-phase and quadrature outputs coupled to said mixers (I,Q) respectively, said mixer circuit () operable to inject and substantially overlap the at least two non-overlapped frequency bands with each other into the IQ IF sections (I,Q) in the IF passband, the IF passband substantially confined to a bandwidth encompassing the thereby-overlapped frequency bands.

Dual frequency receiver with single I/Q IF pair and mixer

An amplifier provided according to an aspect of the present invention includes a set of passive impedances forming a tuned load to a gain stage and also to provide a 180 degrees phase shifted signal of a gain signal received from the gain stage. The output of the gain stage and the 180 degrees phase shifted signal together form a differential amplified signal corresponding to an input signal gained by the gain stage. In an embodiment, the set of passive impedances includes a three terminal centre tapped inductor in combination with a capacitor, together operating as a filter to pass only a desired frequency band. The windings of the inductor may be designed to provide mutual coupling between two portions such that there is a negative correlation between the strength of the received gained signal and the 180 degree phase shifted signal.

Amplifier with single-ended input and differential output

In a method and system for filtering an input signal with a filter included in a phase locked loop (PLL), a unidirectional feedback path is configured from an output of the filter to an input of the filter. The unidirectional feedback path includes a feedback resistor that is configured to adjust a bandwidth of the PLL. A zero path is configured from the output to a voltage reference, such as ground. The zero path includes a capacitor coupled in series with a bias resistor. The bias resistor, which along with the capacitor determines a zero frequency of the filter, is configured to reduce a value of the capacitor without a substantial increase in a phase noise of the PLL due to the unidirectional nature of the feedback. A reduction in the value of the capacitor enables a corresponding reduction in a silicon area to form the capacitor.

Method and apparatus for reducing silicon area of a phase lock loop (PLL) filter without a noise penalty

A digital tuning circuit which generates a digital code representative of a difference of signals generated by a mirror trans-conductor circuit (having electrical characteristics similar to a trans-conductor circuit in a filter) and a reference circuit. The digital code is used to adjust the trans-conductance of both the mirror trans-conductor circuit and the filter. Some of the most/more significant bits may be used to selectively activate the respective trans-conductor elements contained in the mirror trans-conductor circuit and the filter. The remaining bits may be used to fine-tune the trans-conductance of the trans-conductor elements and the filter.

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Bengaluru, India

Saravana Kumar Ganeshan