Lsi Logic Corporation

Sarathy Rajagopalan

Kishor V Desai

Kumar Nagarajan

Maniam B Alagaratnam

Mohan R Nagar

Mukul A Joshi

John Pierre McCormick

Zafer S Kutlu

Minh N Vuong

A packaged integrated circuit including a package substrate having electrical contacts for receiving an integrated circuit. The integrated circuit is electrically connected to the electrical contacts of the package substrate. A stiffener is mounted to the package substrate, where the stiffener has a non-orthogonal cut out in which the integrated circuit is disposed. The edges of the cut out are disposed at no greater a distance from the corners of the integrated circuit than they are from the sides of the integrated circuit.

Integrated circuit package design

A method of assembling at least a first integrated circuit and a second integrated circuit into a multi chip module. The first integrated circuit is attached and electrically connected to a first substrate to form a first assembly, which is tested to ensure that it functions properly. The second integrated circuit is attached and electrically connected to a second substrate to form a second assembly, which is also tested to ensure that it functions properly. The first assembly is attached and electrically connected to the second assembly to form the multi chip module.

Multi chip module assembly

A thermal measurement device for obtaining accurate thermal profiles during flip-chip semiconductor packaging and methodologies for making such devices is disclosed. Particularly, a measurement device comprised of a thermocouple sandwiched between a semiconductor packaging substrate and a semiconductor die. Such a device providing increased accuracy in temperature measurement. The present invention also teaches a packaging substrate assembled with a semiconductor die having an opening in the substrate enabling the placement of a thermocouple such that it is in contact with the die and secured in place. Additionally, methods of constructing the devices of the present invention are disclosed.

Method and apparatus for thermal profiling of flip-chip packages

Integrated circuit package design with non-orthogonal die cut out

A package comprises a top die and a bottom die. The top die has top and bottom surfaces while the bottom die has top and bottom surfaces. The bottom die is mounted on a substrate, which has a top surface, such that the bottom surface of the bottom die faces the top surface of the substrate. The bottom surface of the top die is separated from the top surface of the bottom die by an interposer, which creates a space between the exterior regions of the top surface of the bottom die and the bottom surface of the top die. Each of a plurality of wires, which are electrically connected to the bottom die, runs through this space (i.e. runs between the top surface of the bottom die and the bottom surface of the top die), thereby permitting (if desired) the top die to be at least as large as the bottom die.

Dual chip in package with a wire bonded die mounted to a substrate

A method for creating a die that has some bond pads that are compatible with wire bonding and others that are compatible with solder bonding. A layer of copper is disposed over aluminum bond pads and selectively removed from those bond pads that are desired to be compatible with wire bonding.

Method for manufacturing a dual chip in package with a flip chip die mounted on a wire bonded die

Disclosed is a method of planarizing an array of plastically-deformable electrical contacts on an integrated circuit. An integrated circuit is placed on a plate with an array of plastically-deformable electrical contacts substantially parallel to and facing the plate, thereby creating an assembly. The integrated circuit is placed above the plate such that the weight of the integrated circuit bears down on the array of plastically-deformable electrical contacts. The assembly is then heated sufficiently to cause individual ones of the plastically-deformable electrical contacts to locally soften but not to cause said individual ones of the electrical contacts to liquefy throughout their volumes. The weight of the integrated circuit applies a force to the softened plastically-deformable electrical contacts, thereby resulting in their planarization.

Method of planarizing die solder balls by employing a die's weight

A method for making a flip chip ball grid array (BGA) package includes the step of thinning a die for matching a composite coefficient of thermal expansion to that of a second level board.

Thin form factor flip chip ball grid array

A packaging substrate includes a plurality of bonding pads and a plurality of gutters formed thereon. A die having conductive bumps on an electrically active surface thereof is positioned such that the conductive bumps of the die are electrically connected to the bonding pads of the packaging substrate. An underfill material fills the underfill space between the packaging substrate and the die to complete the structure. The plurality of gutters creates a linear flow front of the underfill material as it flows across the underfill space.

Growing community of inventors

Fremont, CA, United States of America

Sarathy Rajagopalan