Sandisk Technologies Inc.

Cypress Semiconductor Corporation

Western Digital Technologies, Inc.

Sarath Chandran Puthenthermadam

Deepanshu Dutta

Jiahui Yuan

Huai-Yuan Tseng

Yu-Chung Lien

Yi Song

Venkatraman Prabhakar

Long Hinh

Kaveh Shakeri

Longju Liu

Idan Alrod

Dana Lee

Jun Wan

Dengtao Zhao

Navneeth Kankani

Sujjatul Islam

Amul Dhirajbhai Desai

Yihang Liu

Ken Cheah

Yanli Zhang

Zhenming Zhou

Gerrit Jan Hemink

Henry Chin

Chris Avila

Mohan Dunga

Niles Yang

Grishma Shah

Ning Ye

Peng Zhang

Deepak Raghu

Sahil Sharma

Rohit Sehgal

Guirong Liang

Linh Tien Truong

Suresh Kumar Upadhyayula

Phil Reusswig

Long C Pham

Pitamber Shukla

Parth Amin

Xue Bai Pitner

Xiaochen Zhu

Yichao Huang

Akira Okada

Fanqi Wu

Chris Yip

Feng Gao

Chandu Gorla

Jie Liu

Albert Chen

A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to one of a plurality of word lines and disposed in memory holes each coupled to one of a plurality of bit lines. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the plurality of word lines and the memory holes and is configured to read the memory cells in a read operation. The control means is also configured to adjust at least one word line read timing and ramping parameter used during the read operation based on an amount of cycling of the memory cells.

Variable read method for read time performance improvement of non-volatile memory

An apparatus is provided that includes a control circuit coupled to a plurality of non-volatile memory cells. The control circuit is configured to perform a program-verify iteration on a first set of the non-volatile memory cells and a second set of the non-volatile memory cells in a plurality of program loops, determine that at least one of the first set of the non-volatile memory cells and the second set of the non-volatile memory cells verification to a programmed state in a first number of program loops, and compare a difference between the first number of program loops and the second number of program loops to an adaptive maximum loop delta limit. The adaptive maximum loop delta limit varies as a function of temperature.

Early program termination with adaptive temperature compensation

An apparatus is provided that includes a control circuit coupled to a plurality of non-volatile memory cells. The control circuit is configured to perform a program-verify iteration on a first set of the non-volatile memory cells in a plurality of program loops, determine that the first set of the non-volatile memory cells passes verification to a particular programmed state in a first number of program loops, determine a first voltage based on the first number of program loops, add an adaptive voltage offset to the first voltage to obtain a second voltage, and program a second set of the non-volatile memory cells in a plurality of program loops using the second voltage. The adaptive voltage offset varies as a function of temperature.

Apparatus and methods for smart verify with adaptive voltage offset

A non-volatile semiconductor memory device, described herein, comprises a bit line, a source line, a memory string comprising a plurality of memory cells connected in series between the source line and the bit line, and control circuitry coupled to the plurality of memory cells, the source line, and the bit line. The control circuitry is configured to: determine if a program operation is a single-bit program operation or multi-bit program operation; in response to the determination, identify a voltage level to set the source line to during performance of the program operation; and perform the program operation on the memory string, the program operation including setting the source line to the voltage level.

CELSRC voltage separation between SLC and XLC for SLC program average ICC reduction

A non-volatile memory system separately performs a memory operation for multiple sub-blocks of a block in order from previously determined slowest sub-block of the block to a previously determined faster sub-block of the block. As a slower sub-block is more likely to fail, this order of is more likely to identify a failure earlier in the process thereby saving time and reducing potential for a disturb. In some embodiments, the proposed order of operation can be used in conjunction with a programming process that concurrently programs blocks in multiple planes using completion of programming of a fastest plane to a data state as a trigger to test for program failure of other planes to the data state.

Non-volatile memory with optimized operation sequence

An apparatus is provided that includes a block including a word line coupled to a plurality of memory cells, and a control circuit coupled to the word line. The control circuit is configured to program the plurality of memory cells by applying program pulses to the word line in a plurality of program loops, determining a first count of a number of the program loops used to complete programming a first subset of the plurality of memory cells to a first programmed state, first comparing the first count to a corresponding first lower limit and a corresponding first upper limit, and determining whether programming the plurality of memory cells has failed based on a result of the first comparing step.

Early detection of programming failure for non-volatile memory

A memory system performs an erase process for the non-volatile memory cells including performing erase verify for the non-volatile memory cells. The erase verify comprises comparing threshold voltages of the non-volatile memory cells to an erase verify reference voltage and determining whether an amount of the non-volatile memory cells having a threshold voltage greater than the erase verify reference voltage is less than an allowed bit count. During the erase process, the system compares threshold voltages of the non-volatile memory cells to an intermediate reference voltage that is greater than the erase verify reference voltage and determines an amount of non-volatile memory cells having threshold voltages greater than the intermediate reference voltage. The Allowed Bit Count is increased (during the erase process) by the amount of non-volatile memory cells having threshold voltages greater than the intermediate reference voltage.

Non-volatile memory with adapting erase process

A system has been described that performs differential temperature compensation based on a differential between the temperature at time of programming and temperature at time of reading for a set of data. Differential temperature compensation is useful for bulk programming/reading (e.g., many pages of data) and/or programming/reading super pages of data (multiple pages residing on different memory die).

Non-volatile memory with differential temperature compensation for super page programming

A non-volatile semiconductor memory device, described herein, comprises non-volatile storage elements and one or more control circuits in communication with the non-volatile storage elements. The one or more control circuits are configured to, during a program iteration of a program operation, determine whether a program voltage level of the program iteration exceeds a threshold program voltage level and in response to the determination, identify a set of voltage levels to apply to a source line connected to a set of the non-volatile storage elements. The one or more control circuits are further configured to perform the program iteration of the program operation on the set of non-volatile storage elements, where the program iteration includes applying the set of voltage levels to the source line.

Program voltage dependent program source levels

Technology is disclosed herein for detecting grown bad blocks in a non-volatile storage system. A stress test may accelerate stressful conditions on the memory cells and thereby provide for early detection of grown bad blocks. The stress test may include applying a program voltage to a selected word line and a stress voltage that is less than a nominal boosting voltage to a word line adjacent one side of the selected word line. The combination of the program voltage and the stress voltage may generate an e-field that is stronger than an e-field that would be generated in a normal program operation, thereby accelerating the stress on the memory cells. The stress test mat further include programming all of the memory cells to a relatively high threshold voltage, which may create additional stress on the memory cells.

Stress test for grown bad blocks

Non-volatile memory with differential temperature compensation for bulk programming

A memory apparatus and method of operation is provided. The apparatus includes a block having memory cells connected to word lines and arranged in strings and is divided into a first sub-block and a second sub-block each configured to be erased as a whole in an erase operation. The apparatus has a temperature measuring circuit configured to detect an ambient temperature of the apparatus. A control circuit is configured to determine a word line inhibit voltage based on the ambient temperature. The control circuit applies an erase voltage to each of the strings while simultaneously applying a word line erase voltage to the word lines associated with a selected one of the first and second sub-blocks to encourage erasing and the word line inhibit voltage to the word lines associated with an unselected one of the first and second sub-blocks to discourage erasing in the erase operation.

Temperature compensation for unselected sub-block inhibit bias for mitigating erase disturb

A method of performing an erase operation on non-volatile storage is disclosed. The method comprises: applying, in a first erase loop of a plurality of erase loops of the erase operation, a first erase voltage pulse to a set of non-volatile storage elements; determining an upper tail of a threshold voltage distribution of the set of non-volatile storage elements after applying the first erase voltage pulse; determining a second erase voltage pulse based on the upper tail of the threshold voltage distribution of the set of non-volatile storage elements; and applying, in a second erase loop of the plurality of erase loops, the second erase voltage pulse to the set of non-volatile storage elements.

Smart erase scheme

A memory device disclosed herein. The memory device comprises: a memory string including a first select transistor, a memory cell transistor, and a second select transistor connected in series; a bit line connected to one end of the first select transistor; a source line connected to one end of the second select transistor; a first select line connected to a gate of the first select transistor; a word line connected to a gate of the memory cell transistor; a second select line connected to a gate of the second select transistor; and a control circuit configured to perform, before a program operation, a pre-charge operation comprising: applying a voltage to the second select line connected to the gate of the second select transistor to cause gate-induced drain leakage from the second select transistor.

Hole pre-charge scheme using gate induced drain leakage generation

A memory apparatus and method of operation is provided. The apparatus includes a block of memory cells arranged in strings and connected to word lines overlying one another in a stack. The block is divided into first and second sub-blocks programmed as a whole in a sub-block mode and includes a particular group connected to a particular word line. A control circuit determines whether the particular group being read is in the second sub-block when operating in the sub-block mode. The control circuit also determines whether one of the first and second sub-blocks is not programmed based on whether the particular group being read is in the second sub-block. The control circuit applies an adjusted read voltage to the word lines of the one of the first and second sub-blocks while reading the particular group based on whether the one of the first and second sub-blocks is not programmed.

Peak and average current reduction for sub block memory operation

Growing community of inventors

Milpltas, CA, United States of America

Sarath Chandran Puthenthermadam