Microsoft Technology Licensing, LLC

Saransh Jain

Michael Scott McIlvaine

Rami Mohammad Al Sheikh

Daren Eugene Streett

Somasundaram Arunachalam

Accelerating fetch target queue (FTQ) processing is disclosed herein. In some aspects, a processor comprises an FTQ and an FTQ acceleration cache (FAC), and is configured to generate a FAC entry corresponding to an FTQ entry of a plurality of FTQ entries of the FTQ, wherein the FTQ entry comprises a fetch address bundle comprising a plurality of sequential virtual addresses (VAs), and the FAC entry comprises metadata for the FTQ entry. The processor is further configured to receive, using the FTQ, a request to access the FTQ entry. The processor is also configured to, responsive to receiving the request to access the FTQ entry, locate, using the FAC, the FAC entry corresponding to the FTQ entry among a plurality of FAC entries of the FAC. The processor is additionally configured to perform accelerated processing of the request to access the FTQ entry using the metadata of the FAC entry.

Accelerating fetch target queue (FTQ) processing in a processor

Selectively updating branch predictors for loops executed from loop buffers is disclosed herein. In some aspects, a branch predictor update circuit of a processor is configured to detect a loop comprising a plurality of loop instructions in an instruction stream, and to determine that the loop is stored within a loop buffer circuit of the processor. The branch predictor update circuit is further configured to determine a count of potential history register updates to the history register for the plurality of loop instructions, and to determine whether the count of potential history register updates exceeds a size of the history register. The branch predictor update circuit is also configured to, responsive to determining that the count of potential history register updates does not exceed the size of the history register, update a branch predictor of the branch predictor circuit based on the plurality of loop instructions.

Selectively updating branch predictors for loops executed from loop buffers in a processor

Providing extended branch target buffer (BTB) entries for storing trunk branch metadata and leaf branch metadata is disclosed herein. In one aspect, a processor comprises a BTB circuit comprising a BTB comprising a plurality of extended BTB entries. The BTB circuit is configured to store trunk branch metadata for a first branch instruction in an extended BTB entry of the plurality of extended BTB entries, wherein the extended BTB entry corresponds to a first aligned memory block containing an address of the first branch instruction. The BTB circuit is also configured to store leaf branch metadata for a second branch instruction in the extended BTB entry in association with the trunk branch metadata, wherein an address of the second branch instruction is subsequent to a target address of the first branch instruction within a second aligned memory block.

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Raleigh, NC, United States of America

Saransh Jain