Xilinx, Inc.

Sarajuddin Niazi

Suresh Ramalingam

Hong Shi

Paul Y Wu

Raymond E Anderson

Siow Chek Tan

An interface layout for a vertical interface of a first semiconductor component is disclosed. A first one or more conductors configured to carry power signals extends vertically from the first semiconductor component. A second one or more conductors configured to carry data signals extends vertically from the first semiconductor component. A third one or more conductors configured to carry ground signals extending vertically from the first semiconductor component. The first one or more conductors are further configured to shield and separate the second one or more conductors. A fourth one or more conductors extends horizontally from the first one or more conductors adjacent to and terminating proximal to the third one or more conductors. A fifth one or more conductors extending horizontally from the third one or more conductors adjacent to and terminating proximal to the first one or more conductors and the fourth one or more conductors. The fourth one or more conductors and the corresponding adjacent fifth one or more conductors form a plate capacitor.

Power-ground co-reference transceiver structure to deliver ultra-low crosstalk

An apparatus for placement between a package and an integrated circuit board includes: an insert having: a substrate having a top side and a bottom side; a first set of pads at the top side of the substrate; a second set of pads at the bottom side of the substrate; and a plurality of vias in the substrate, the vias connecting respective pads in the first set to respective pads in the second set; wherein the insert has a thickness that is less than a spacing between the package and the integrated circuit board.

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Union City, CA, United States of America

Sarajuddin Niazi