Siltronic Ag

Imec Vzw

Ihp Gmbh-innovations for High Performance Microelectronics/leibniz-institut Fur Innovative Mikroelektronik

Sarad Bahadur Thapa

Peter Storck

Brian Murphy

Thomas Schroeder

Norbert Werner

Ming Zhao

Maik Haeberlen

Martin Vorderwestner

Helmut Schwenk

Frank Muemmler

Rudolf Mayrhuber

Lidia Tarnawska

Peter Dreier

Ute Rothammer

Guenter Sachs

Marvin Zoellner

Thomas Schröder

Maik HÄBERLEN

Marvin ZÖLLNER

Frank Mümmler

Günter Sachs

A heteroepitaxial wafer comprises, in the following order: a silicon substrate having a diameter and a thickness;

Heteroepitaxial wafer and method for producing a heteroepitaxial wafer

Problems associated with the mismatch between a silicon substrate and a group-IIIA nitride layer are addressed by employing a silicon substrate processed to have a surface comprising closely spaced tips extending from the surface, depositing a group-IIIB silicide layer on the tips, then depositing a group-IIIB nitride layer, and then depositing a group-IIIA nitride.

Semiconductor wafer comprising a monocrystalline group-IIIA nitride layer

A layered semiconductor substrate has a monocrystalline first layer based on silicon, having a first thickness and a first lattice constant adetermined by a first dopant element and a first dopant concentration, and in direct contact therewith, a monocrystalline second layer based on silicon, having a second thickness and a second lattice constant a, determined by a second dopant element and a second dopant concentration, and a monocrystalline third layer comprising a group III nitride, the second layer located between the first layer and the third layer, wherein a&#x3e;a, wherein the crystal lattice of the first layer and the second layer are lattice-matched, and wherein the bow of the layered semiconductor substrate is in the range from &#x2212;50 &#x3bc;m to 50 &#x3bc;m.

Layered semiconductor substrate with reduced bow having a group III nitride layer and method for manufacturing it

A semiconductor wafer has a silicon single crystal substrate having a top surface and a stack of layers covering the top surface, the stack of layers containing an AlN nucleation layer covering the top surface of the silicon single crystal substrate, wherein the top surface of the silicon single crystal substrate has a crystal lattice orientation which is off-oriented with respect to the {111}-plane, the normal to the top surface being inclined with respect to the &#x3c;111&#x3e;-direction toward the &#x3c;11-2&#x3e;-direction by an angle &#x3b8; of not less than 0.3&#xb0; and not more than 6&#xb0;, the azimuthal tolerance of the inclination being &#xb1;0.1&#xb0;; and an AlGaN buffer layer which covers the AlN nucleation layer and contains one or more AlGaN layers, wherein 0&#x3c;&#xd7;&#x3c;1.

Semiconductor wafer and a method for producing the semiconductor wafer

A semiconductor wafer contains the following layers in the given order:

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Growing community of inventors

Burghausen, Germany

Sarad Bahadur Thapa