Intel Corporation

Sara S Baghsorkhi

Altug Koker

Abhishek R Appu

Justin E Gottschlich

Joydeep Ray

Dukhwan Kim

Balaji Vembu

Elmoustapha Ould-Ahmed-Vall

Kamal Sinha

Linda L Hurd

Eriko Nurvitadhi

Rajkishore Barik

Prasoonkumar Surti

John Charles Weast

Ben J Ashbaugh

Nicolas C Galoppo Von Borries

Xiaoming Chen

Tsung-Han Lin

Kevin Nealis

Narayan Srinivasa

Feng Chen

Anbang Yao

Nadathur Rajagopalan Satish

Farshad Akhbari

Mike B Macpherson

Albert Hartono

Chandrasekaran Sakthivel

Liwei Ma

Nalini Vasudevan

Ping Tak Tang

Travis T Schluessler

Barath Lakshmanan

Jayashankar Bharadwaj

Subramaniam M Maiyuran

Karthik Vaidyanathan

Adam T Lake

John H Feit

Jeffery S Boles

Devan Burke

Wenyin Fu

Josh B Mastronarde

Michael S Strickland

Victor W Lee

Daehyun Kim

Vasanth Ranganathan

Sanjeev S Jahagirdar

Cheng C Wang

Youfeng Wu

Jeremy Bottleson

Alexander F Heinecke

Mohammad R Haghighat

Robert Valentine

Shengtian Zhou

Mohammad Mejbah Ul Alam

Mark Jay Charney

Christopher J Hughes

Tatiana Shpeisman

Tin-Fook Ngai

Dhawal Srivastava

Milind Baburao Girkar

Jason Martin

David M Durham

Kshitij Arun Doshi

Ravi L Sahita

Mohan J Kumar

Kathiravetpillai Sivanesan

Baiju V Patel

Ankur N Shah

Ravishankar Iyer

Bahareh Sadeghi

Michael Lemay

Andrew J Herdrich

Ignacio Javier Alvarez

Jr-Shian Tsai

Narayan Biswal

Liuyang L Yang

Stanley J Baran

David Israel Gonzalez Aguirre

Menachem Adelman

Mats Gustav Agerstam

Vadim Sukhomlinov

Jonathan Kennedy

Mingqiu Sun

Alexander Bachmutsky

Gokcen Cilingir

Nilesh V Shah

Barnan Das

Ian M Steiner

Sridhar G Sharma

Marcos Emanuel Carranza

Archie Sharma

Jeffrey D Chamberlain

Mayuresh M Varerkar

Nilesh K Jain

Eric Dahlen

Mingwei Zhang

Evangelos Georganas

Amin Firoozshahian

Robert Colby

Maria E Ramirez Loaiza

One embodiment provides for a compute apparatus comprising a decode unit to decode a single instruction into a decoded instruction that specifies multiple operands including a multi-bit input value and a one-bit weight associated with a neural network, as well as an arithmetic logic unit including a multiplier, an adder, and an accumulator register. To execute the decoded instruction, the multiplier is to perform a fused operation including an exclusive not OR (XNOR) operation and a population count operation. The adder is configured to add the intermediate product to a value stored in the accumulator register and update the value stored in the accumulator register.

Compute optimizations for neural networks

An apparatus to facilitate optimization of a neural network (NN) is disclosed. The apparatus includes optimization logic to define a NN topology having one or more macro layers, adjust the one or more macro layers to adapt to input and output components of the NN and train the NN based on the one or more macro layers.

Neural network optimization mechanism

One embodiment provides a general-purpose graphics processing unit comprising a dynamic precision floating-point unit including a control unit having precision tracking hardware logic to track an available number of bits of precision for computed data relative to a target precision, wherein the dynamic precision floating-point unit includes computational logic to output data at multiple precisions.

Compute optimizations for low precision machine learning operations

Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.

Compute optimization mechanism for deep neural networks

Methods, apparatus, systems, and articles of manufacture are disclosed herein that mitigate hard-braking events. An example apparatus at least one memory; instructions; and processor circuitry to execute the instructions to: determine a danger level associated with an object, the danger level indicative of a first measure of damage corresponding to a trajectory of the object compared to a trajectory of a vehicle; determine, based on the first danger level, a danger measure based on at least one of a position of the object, a velocity of the object, an acceleration of the object, a direction of travel of the object, a weight or mass of the object; and generate instructions to transmit to a steering system or a braking system of the vehicle based on the determination.

Methods and apparatus to mitigate hard-braking events

One embodiment provides a multi-chip module accelerator usable to execute tensor data processing operations a multi-chip module. The multi-chip module may include a memory stack including multiple memory dies and parallel processor circuitry communicatively coupled to the memory stack. The parallel processor circuitry may include multiprocessor cores to execute matrix multiplication and accumulate operations. The matrix multiplication and accumulate operations may include floating-point operations that are configurable to include two-dimensional matrix multiply and accumulate operations involving inputs that have differing floating-point precisions. The floating-point operations may include a first operation at a first precision and a second operation at a second precision. The first operation may include a multiply having at least one 16-bit floating-point input and the second operation may include an accumulate having a 32-bit floating-point input.

Embodiments for gathering and scattering matrix data by row are disclosed. In an embodiment, a processor includes a storage matrix, a decoder, and execution circuitry. The decoder is to decode an instruction having a format including an opcode field to specify an opcode and a first operand field to specify a set of irregularly spaced memory locations. The execution circuitry is to, in response to the decoded instruction, calculate a set of addresses corresponding to the set of irregularly spaced memory locations and transfer a set of rows of data between the storage and the set of irregularly spaced memory locations.

Matrix data scatter and gather between rows and irregularly spaced memory locations

One embodiment provides a parallel processor comprising a hardware scheduler to schedule pipeline commands for compute operations to one or more of multiple types of compute units, a plurality of processing resources including a first sparse compute unit configured for input at a first level of sparsity and hybrid memory circuitry including a memory controller, a memory interface, and a second sparse compute unit configured for input at a second level of sparsity that is greater than the first level of sparsity.

Programmable coarse grained and sparse matrix compute hardware with advanced scheduling

Systems, apparatuses and methods may provide for technology that detects a tensor operation in an application, wherein the tensor operation has an unspecified tensor input size, determines the input tensor size at runtime, and selects a partition configuration for the tensor operation based at least in part on the input tensor size and one or more runtime conditions. In one example, the technology searches a lookup table for the input tensor size and at least one of the runtime condition(s) to select the partition configuration.

Unified programming interface for regrained tile execution

One embodiment provides for a general-purpose graphics processing unit including a scheduler to schedule multiple matrix operations for execution by a general-purpose graphics processing unit. The multiple matrix operations are determined based on a single machine learning compute instruction. The single machine learning compute instruction is a convolution instruction and the multiple matrix operations are associated with a convolution operation.

Specialized fixed function hardware for efficient convolution

Systems, apparatuses and methods may provide for technology that detects a generic cloud service call in an application, wherein platform-specific parameters are unspecified in the cloud service call. The technology may also select a first cloud platform based on one or more performance constraints associated with the first cloud platform and automatically generate a first platform-specific service call based on the cloud service call and the first set of parameters. In one example, the technology also maps the cloud service call to the first platform-specific service call. Additionally, the technology may migrate the cloud service call to a second cloud platform without rewriting the generic cloud service call.

Unified programming model for function as a service computing

One embodiment provides an apparatus comprising a memory stack including multiple memory dies and a parallel processor including a plurality of multiprocessors. Each multiprocessor has a single instruction, multiple thread (SIMT) architecture, the parallel processor coupled to the memory stack via one or more memory interfaces. At least one multiprocessor comprises a multiply-accumulate circuit to perform multiply-accumulate operations on matrix data in a stage of a neural network implementation to produce a result matrix comprising a plurality of matrix data elements at a first precision, precision tracking logic to evaluate metrics associated with the matrix data elements and indicate if an optimization is to be performed for representing data at a second stage of the neural network implementation, and a numerical transform unit to dynamically perform a numerical transform operation on the matrix data elements based on the indication to produce transformed matrix data elements at a second precision.

Embodiments of systems, apparatuses and methods provide enhanced function as a service (FaaS) to users, e.g., computer developers and cloud service providers (CSPs). A computing system configured to provide such enhanced FaaS service include one or more controls architectural subsystems, software and orchestration subsystems, network and storage subsystems, and security subsystems. The computing system executes functions in response to events triggered by the users in an execution environment provided by the architectural subsystems, which represent an abstraction of execution management and shield the users from the burden of managing the execution. The software and orchestration subsystems allocate computing resources for the function execution by intelligently spinning up and down containers for function code with decreased instantiation latency and increased execution scalability while maintaining secured execution. Furthermore, the computing system enables customers to pay only when their code gets executed with a granular billing down to millisecond increments.

Function as a service (FaaS) system enhancements

In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

Dynamic distributed training of machine learning models

Growing community of inventors

San Jose, CA, United States of America

Sara S Baghsorkhi