Lawrence Livermore National Security, LLC

Other

University of California

Sara Elizabeth Harrison

Lars F Voss

Rebecca J Nikolic

Qinghui Shao

Adam M Conway

Clint Frye

Srabanti Chowdhury

Tiziana C Bond

Victor V Khitrov

Ishwara B Bhat

Alexander Peter Povilus

Joseph Devin Schneider

Caitlin Anne Chapin

Catherine E Reinhardt

Noah Patrick Allen

John Berns Lancaster

Laura Leos

Payal Kamlesh Singh

Daniel Max Dryden

Devices, methods and techniques related to photoconductive switches using diamond are disclosed. In one example aspect, a photoconductive apparatus includes a diamond layer positioned to receive a light. The diamond layer is doped with nitrogen. The apparatus also includes a first electrode coupled to the diamond layer to provide a first electrical contact for the diamond layer, and a second electrode coupled to the diamond layer to provide a second electrical contact for the diamond layer and configured to reflect the light back to the diamond layer. The first electrode and the second electrode are configured to establish an electric field across the diamond layer in response to receiving the light.

Photoconductive switch with diamond

An apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate including a first semiconductor material, an array of three dimensional (3D) structures above the substrate, a sidewall heterojunction layer positioned on at least one vertical sidewall of each 3D structure, and an isolation region positioned between the 3D structures. Each 3D structure includes the first semiconductor material. The sidewall heterojunction layer includes a second semiconductor material, where the first and second semiconductor material have different bandgaps.

Three dimensional vertically structured electronic devices

In one embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate comprising a semiconductor material, an array of three dimensional (3D) structures above the substrate, a gate region, and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, the second region including a portion of at least one vertical sidewall of the 3D structure. The gate region is present on a portion of an upper surface of the second region and the gate region is coupled to a portion of the at least one vertical sidewall of each 3D structure.

The present disclosure relates to a method of forming a tapered optical fiber, where the optical fiber has a cladding encasing a core and has an initial outer diameter. The method involves applying opposing forces to spaced apart sections of the optical fiber. The spaced apart sections define a length portion representing a waist region. While applying the opposing forces, simultaneously applying heat to the waist region to gradually produce a taper of the optical fiber within the waist region. The taper has a first diameter at a midpoint of the waist region which is less than the initial outer diameter. An etch operation is then performed by chemically etching at least a subportion of the waist region of the optical fiber to reduce the subportion to a second diameter which is less than the first diameter.

Method for fast and efficient fiber tapering

According to one embodiment, a method includes performing a plasma etching process on a masked III-V semiconductor, and forming a passivation layer on etched portions of the III-V semiconductor. The passivation layer includes at least one of a group III element and/or a metal from the following: Ni, Cr, W, Mo, Pt, Pd, Mg, Ti, Zr, Hf, Y, Ta, and Sc.

Metal-based passivation-assisted plasma etching of III-v semiconductors

In one embodiment, a method of forming a vertical transistor includes forming a layer comprising a semiconductor material above a substrate, defining three dimensional (3D) structures in the layer, forming a second region in at least one vertical sidewall of each 3D structure, and forming an isolation region between the 3D structures. In another embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate comprising a semiconductor material, an array of 3D structures above the substrate, and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, the second region including a portion of at least one vertical sidewall of the 3D structure.

According to one embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate including a semiconductor material; an array of three dimensional (3D) structures above the substrate; and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, where the second region includes a portion of at least one vertical sidewall of the 3D structure.

In one embodiment, a product includes a structure comprising a material of a Group-III-nitride having a dopant, where a concentration of the dopant in the structure has a concentration gradient characteristic of diffusion of the dopant inward from at least a portion of a surface of the structure in a direction substantially normal to the portion of the surface. The structure has less than 1% decomposition of the Group-III-nitride at the surface of the structure.

Gallidation assisted impurity doping

According to one embodiment, an apparatus includes a substrate, and at least one three dimensional (3D) structure above the substrate. The substrate and the 3D structure each include a semiconductor material. The 3D structure also includes: a first region having a first conductivity type, and a second region coupled to a portion of at least one vertical sidewall of the 3D structure.

Three dimensional vertically structured MISFET/MESFET

In one embodiment, an apparatus includes: a first layer including a n+ dopant or p+ dopant; an intrinsic layer formed above the first layer, the intrinsic layer including a planar portion and pillars extending above the planar portion, cavity regions being defined between the pillars; and a second layer deposited on a periphery of the pillars thereby forming coated pillars, the second layer being substantially absent on the planar portion of the intrinsic layer between the coated pillars. The second layer includes an n+ dopant when the first layer includes a p+ dopant. The second layer includes a p+ dopant when the first layer includes an n+ dopant. The apparatus includes a neutron sensitive material deposited between the coated pillars and above the planar portion of the intrinsic layer. In additional embodiments, an upper portion of each of the pillars includes a same type of dopant as the second layer.

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Fremont, CA, United States of America

Sara Elizabeth Harrison