Intel Corporation

Sapumal Wijeratne

Sanu K Mathew

Mark A Anders

Hans J Greub

Ram K Krishnamurthy

Stephen H Gunther

Alexander Gendler

Tod F Schiff

Alexander Uan-Zo-Li

Mark J Gallina

Clifford L Ong

Jianwei Dai

Nimrod Angel

Ameya Ambardekar

Eric Kwesi Donkoh

Daniel J Deleganes

Marijan Persun

Mark D Nardin

Pankaj Aswal

Vikas Vij

Mohammad M Haq

Anandraj Devarajan

Seung H Hwang

Mahesh Kumar P

Matthew W Ernest

Somvir Singh Dahiya

Brian A Kuns

Nanda Siddaiah

An apparatus and method for temperature-constrained frequency control and scheduling. For example, one embodiment of a processor comprises: a plurality of cores; power management circuitry to control a frequency of each core of the plurality of cores based, at least in part, on a temperature associated with one or more cores of the plurality of cores, the power management circuitry comprising: a temperature limit-driven frequency controller to determine a first frequency limit value based on a temperature of a corresponding core reaching a first threshold; frequency prediction hardware logic to predict a temperature-constrained frequency of the corresponding core based on the first frequency limit value and an initial frequency limit value; and performance determination hardware logic to determine a new performance value for the corresponding core based on the temperature-constrained frequency, the new performance value to be provided to a task scheduler.

Apparatus and method for temperature-constrained frequency control and scheduling

A dedicated pin of a processor or system-on-chip (SoC) is used to indicate whether power level (e.g., charge, voltage, and/or current) of a battery falls below a threshold. The threshold can be predetermined or programmable. The battery is used to provide power to the processor and/or SoC. Upon determining that the power level of the battery falls below the threshold, the processor by-passes the conventional process of entering low performance or power mode, and directly throttles voltage and/or operating frequency of the processor. This allows the processor to continue to operate at low battery power. The fast transition (e.g., approximately 10 &#x3bc;S) from an active state to a low performance or power mode, in accordance with a logic level of the voltage on the dedicated pin, reduces decoupling capacitor design requirements, and makes it possible for the processor to adapt higher package power control settings (e.g., PL4).

Fast dynamic capacitance, frequency, and/or voltage throttling apparatus and method

Provided is a novel keeper circuit with a pull-up device whose strength changes for different operating supply levels so that the pull-up device is weaker for smaller supply levels and stringer for higher supply levels.

Keeper circuit

A method and system to lower the minimum operating voltage of a register file without increasing the area of each bit cell of the register file. In one embodiment of the invention, the register file is coupled to logic that reduces the contention between the NMOS devices and the PMOS devices in each bit cell of the register file during write and/or read operations of the register file. By doing so, the register file is able to operate at a lower minimum operating voltage.

Method and system to lower the minimum operating voltage of register files

A method and system to allow reduction of leakage in the bit lines of a memory device. In addition, minimal delay to the bit lines is introduced by the method and system. The memory device has a plurality of bit lines and a plurality of nodes to facilitate access of a respective one of the bit lines. A logic circuit that has a plurality of transistors and each transistor is coupled with the respective one of the bit lines and with a respective one of the nodes to reduce leakage of the bit lines when the transistors are deactivated. A just in time pre-charge method is also used to avoid the requirement of an additional pre-charge device to prevent excessive charge sharing while enabling the reduction of leakage of the bit lines.

Method and apparatus for reducing leakage in bit lines of a memory device

Methods and apparatus to provide ultra low voltage, low leakage, high density, and/or variation tolerant memory bit cells are described. In one embodiment, each of the cross-coupled invertors of a memory cell may include a plurality of p-channel transistors. Other embodiments are also described.

Ultra low voltage, low leakage, high density, variation tolerant memory bit cells

A multi-bit adder includes a carry chain, a carry-skip network, sum cells, and a carry-sum cell. The carry chain propagates, generates, or kills carry-in bits. The carry-skip network is coupled to the carry chain to selectively skip the carry-in bits over at least one portion of the carry chain. The sum cells are coupled along the carry chain to sum the carry-in bits with corresponding bits of two operands to generate a multi-bit resultant. The carry-sum cell is coupled to receive one of the carry-in bits to a single intermediate bit position on the carry chain and to generate one bit of the multi-bit resultant having a more significant bit position than the single intermediate bit position.

Carry-skip adder having merged carry-skip cells with sum cells

An adder circuit is provided that includes a propagate and generate circuit stage to provide propagate and generate signals, a plurality of carry-merge stages to provide carry signals based on the propagate and generate signals and a conditional sum generator to provide conditional sums based on the propagate and generate signals. The conditional sum generator includes ripple carry gates and XOR logic gates. The adder circuit also includes a plurality of multiplexers to receive the carry signals and the conditional sums and to provide an output based on the input signals.

Sparse tree adder circuit

An adder circuit includes a number of selectors and an adder. The selectors feed the adder with multiple input data bits. Each of the selectors includes a combination of a multiplexing network and a sense amplifier to select from a number of input values to generate the multiple input data bits. The combination of the multiplexing network and the sense amplifier acts as the state-holding element at the input of the adder, avoiding the overheads of an explicit latch stage.

Adder circuit with sense-amplifier multiplexer front-end

A circuit comprises an evaluate clock trace to receive an evaluate clock signal and a precharge clock trace to receive a precharge clock signal. The circuit further comprises sample circuitry coupled to a first signal trace, a second signal trace, the precharge clock trace and the evaluate clock trace to facilitate a detection of a transition on the first signal trace from a first voltage level to a second voltage level. In addition, the circuit comprises latch circuitry coupled to the first signal trace, the second signal trace, the precharge clock trace and the evaluate clock trace to utilize at least a portion of the sample circuitry to maintain voltage levels on the first and the second signal traces when an evaluate clock and a precharge clock are inactive.

Single stage level restore circuit with hold functionality

A ratioed logic gate includes a contention interrupt circuit. The ratioed logic gate includes a pull up network coupled to a pull down network. Multiple inputs are coupled to turn the pull down and pull up networks on and off. An output is coupled to apply a logical function on the multiple inputs. A contention interrupt circuit is coupled to one of the pull up and the pull down networks to open circuit the one of the pull up and pull down networks when the pull up and pull down networks are in contention.

Ratioed logic circuits with contention interrupt

A register file includes a dynamic local bit trace, a plurality of data cells coupled to the dynamic local bit trace, and a device coupled to the dynamic local bit trace to facilitate precharging the dynamic local bit trace to a precharge value and to intelligently hold the precharged value on the dynamic local bit trace during evaluation of the dynamic local bit trace.

Leakage tolerant register file

A circuit comprises a signal trace to receive a first large signal, a first plurality of signal traces to receive a small signal pair and a clock trace to receive a clock signal. The circuit further comprises a mixed signal circuit having at least a first and a second element, coupled to the signal trace, the first plurality of signal traces and the clock trace. The mixed signal circuit it to facilitate generation of a second large signal based at least in part on the small signal pair and the first large signal, with the first large signal and the clock signal driving the first and second elements respectively to transition asynchronously.

Single stage, level restore circuit with mixed signal inputs

An apparatus comprising a low voltage swing (LVS) circuit having a plurality of alternating LVS pre-charging and evaluation phases and a select logic circuit coupled to the LVS circuit and responsive to a plurality of input data signals to generate a plurality of select signals for the LVS circuit. Each of the select signals occurs during one of the LVS evaluation phases and has a turning-on edge and a turning-off edge. The turning-off edge of each of the select signals is generated independent of the input data signals.

Select logic for low voltage swing circuits

In one embodiment, the invention is a method. The method includes extracting parameters of a set of domino logic circuits. The method also includes simulating each domino logic circuit of the set of domino logic circuits. Also, the method includes reporting results of the simulation.

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Portland, OR, United States of America

Sapumal Wijeratne