National Technology & Engineering Solutions of Sandia, LLC

Sapan Agarwal

Matthew Marinella

Albert Alec Talin

Elliot James Fuller

James Bradley Aimone

Conrad D James

Tu-Thach Quach

Alexander H Hsia

Farid El Gabaly Marquez

Christopher Michael

A radiation-hardened (rad-hard) computing system can include a rad-hard processor, a second processor, and a memory operably coupled to the rad-hard processor. The rad-hard processor can cause the second processor to execute compute-intensive tasks that can be performed more quickly or with fewer computing resources by the second processor than the rad-hard processor. The rad-hard processor can selectively cause the second processor to execute a compute-intensive task based upon determining that the second processor is in a normal operating state. The rad-hard processor can further evaluate computing results generate by the second processor to determine whether such computing results meet an applicable acceptability condition. The rad-hard processor can employ a computing result that meets an applicable acceptability condition in further computing operations.

Heterogeneous radiation-hardened computing system

An array circuit includes a plurality of vector-matrix multiplication (VMM) elements arranged in rows and columns. The VMM elements are configured to collectively perform multiplication of an input vector by a programmed input matrix to generate a plurality of output values that are representative of a result matrix that is the result of multiplication of the input vector and the input matrix. The VMM elements store states of the input matrix. Input voltages to the array are representative of elements of the input vector. A VMM element draws charge from a column read line based upon charging of a capacitor in the VMM. An integrator circuit connected to the column read line outputs a voltage that is indicative of a total charge drawn from the column read line by elements connected to the read line, which voltage is further indicative of an element of a result matrix.

Analog vector-matrix multiplication by capacitive elements with resistive state storage

A two-terminal memory device and methods for its use are provided. In the device, a bottom electrode is electrically continuous with a first operating terminal, and a control gate electrode is electrically continuous with a second operating terminal. A stack of insulator layers comprising a hopping conduction layer and a tunnel layer is contactingly interposed between the bottom electrode and the control gate electrode. The tunnel layer is thinner than the hopping conduction layer, and it has a wider bandgap than the hopping conduction layer. The hopping conduction layer consists of a material that supports electron hopping transport.

Two-terminal electronic charge resistance switching device

A method and apparatus for processing data. The data is sent to a processor unit comprising a group of neural cores, a group of digital processing cores, and a routing network connecting the group of digital processing cores. The data is processed in the processor unit to generate a result.

Mixed core processor unit

A method and system for accessing a memory for a data processing system. The method comprises sending a read request for a plurality of locations in the memory to read the plurality of locations in parallel based on an upper bound for reading the memory. The upper bound for a number of locations is based on a group of constraints for the memory. The method receives a summed value of a plurality of memory values in the plurality of locations in the memory.

Memory access system

A non-volatile memory device is described herein. The non-volatile memory device includes a diffusive memristor electrically coupled to a redox transistor. The redox transistor includes a gate, a source, and a drain, wherein the gate comprises a first storage element that acts as an ion reservoir, and a channel between the source and the drain comprises a second storage element, wherein a state of the memory device is represented by conductance of the second storage element.

Ionic floating-gate memory device

A method for programming substantially simultaneously more than one of the three-terminal memory cells that represent the values of a matrix to be multiplied by a vector is disclosed. Programming may be achieved by controlling the gate-drain voltage for more than one cell simultaneously to change each such cell's physical state and hence its effective resistance. Illustratively, the gates of each row of the cells corresponding to the matrix are coupled together and each coupled row is coupled to a respective controllable voltage source while the drains of each column of the cells of the matrix are coupled together and each coupled column is coupled to a respective controllable voltage source. The controllable voltage sources are arranged so that at the intersection of a row and a column, a cell experiences one of three conditions: increase effective resistance, decrease effective resistance, or substantially no change.

Circuit arrangement and technique for setting matrix values in three-terminal memory cells

Various technologies pertaining to a transistor having a variable-conductance channel with a non-volatile tunable conductance are described herein. The transistor comprises source and drain electrodes separated by a conducting channel layer. The conducting channel layer is separated from an electrochemical gate (ECG) layer by an electrolyte layer that prevents migration of electrons between the channel and the ECG but allows ion migration. When a voltage is applied between the channel and the ECG, electrons flow from one to the other, which causes a migration of ions from the channel to the ECG or vice versa. As ions move into or out of the channel layer, the conductance of the channel changes. When the voltage is removed, the channel maintains its conductance state.

Tunable ionic electronic transistor

Various technologies for improving uniformity of operation of elements in an array circuit are described herein. In an exemplary embodiment, a plurality of resistive elements are incorporated into an array circuit such that voltages developed across any two elements is substantially the same when an equal voltage is applied to energize the elements. In a crossbar array circuit that comprises a plurality of elements arranged in rows and columns, the resistance of each of the resistive elements is based upon a row or column to which the resistive element is connected.

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Dublin, CA, United States of America

Sapan Agarwal