Intel Corporation

Marvell International Limited

Sanu K Mathew

Sudhir K Satpathy

Vikram B Suresh

Ram K Krishnamurthy

Raghavan Kumar

Mark A Anders

Vinodh Gopal

Himanshu Kaul

Rafael Misoczki

Manoj R Sastry

Santosh Ghosh

James D Guilford

Abhishek R Appu

Joydeep Ray

Altug Koker

Balaji Vembu

Vasanth Ranganathan

Sanjeev S Jahagirdar

Kamal Sinha

Anbang Yao

Eriko Nurvitadhi

Nicolas C Galoppo Von Borries

Tatiana Shpeisman

Xiaoming Chen

Rajkishore Barik

Ping Tak Tang

Tsung-Han Lin

Michael S Strickland

Andrew H Reinders

Shay Gueron

Steven Hsu

Jiangtao Li

Farhana Sheikh

Kirk S Yap

Michael E Kounavis

Anand Rajan

Jesse R Walker

Patrick Koeberl

Rajaraman Ramanarayanan

Ernie F Brickell

Sean M Gulley

Amit Agarwal

David Johnston

Manoj Sachdev

Sapumal Wijeratne

Roel Maes

Vasantha K Erraguntla

Gilbert M Wolrich

Vivek K De

Wajdi K Feghali

Gregory Kengho Chen

Wei Wu

Krishnamurthy Soumyanath

Harish Krishnamurthy

William C Hasenplaugh

Zeshan A Chishti

George W Cox

Rosario Cammarota

Rachael Jade Parker

Suresh Srinivasan

Neeraj S Upasani

Jason Sandri

Zheng Guo

Simon N Peffers

Xiaosen Liu

Avinash Laxmisha Varna

Sarvesh H Kulkarni

Gregory M Iovino

Kevin Gotze

Shashank Shekhar

Randy L Allmon

David L Harris

Tao Zhou

Sachin Taneja

Amitkumar Patel

Arvind Singh

Jonathan Enoch

Vishak Venkatraman

Nanda Siddaiah

Hoang Q Dao

In one embodiment, a method comprises: combining, in a first adder circuit of a cryptographic engine, a round key with masked plaintext to generate an additively masked input; converting, in a first converter of the cryptographic engine, the additively masked input to a multiplicatively masked input; and performing, in a substitution box circuit of the cryptographic engine, a non-linear inverse operation on the multiplicatively masked input when the multiplicatively masked input is non-zero, and performing the non-linear inverse operation on a random non-zero value when the multiplicatively masked input is zero. Other embodiments are described and claimed.

Side-channel resistant multiplicatively masked encryption engine with zero-value attack detection

Methods and apparatus relating to techniques utilizing fine-grained bitcoin engine deactivation for yield recovery, performance, and/or power management are described. In an embodiment, a configurable compute tile comprising a plurality of cryptocurrency mining engines. Logic circuitry causes deactivation of one or more cryptocurrency mining engines from the plurality of cryptocurrency mining engines based at least in part on a request for deactivation of the one or more cryptocurrency mining engines. The logic circuitry adjusts a nonce search resolution for one or more active cryptocurrency mining engines of the plurality of cryptocurrency mining engines in response to the request for deactivation. Other embodiments are also disclosed and claimed.

Fine-grained bitcoin engine deactivation for yield recovery, performance, and/or power management

Technologies for memory and I/O efficient operations on homomorphically encrypted data are disclosed. In the illustrative embodiment, a cloud compute device is to perform operations on homomorphically encrypted data. In order to reduce memory storage space and network and I/O bandwidth, ciphertext blocks can be manipulated as data structures, allowing operands for operations on a compute engine to be created on the fly as the compute engine is performing other operations, using orders of magnitude less storage space and bandwidth.

Technologies for memory and I/O efficient operations on homomorphically encrypted data

One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute an intermediate product of 16-bit operands and to compute a 32-bit sum based on the intermediate product.

Instructions and logic to perform floating point and integer operations for machine learning

One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute a 32-bit intermediate product of 16-bit operands and to compute a 32-bit sum based on the 32-bit intermediate product.

In one example an apparatus comprises a computer readable memory, an XMSS verification manager logic to manage XMSS verification functions, a one-time signature and public key generator logic, a chain function logic to implement chain function algorithms, a low latency SHA3 hardware engine, and a register bank communicatively coupled to the XMSS verification manager logic. Other examples may be described.

Low latency post-quantum signature verification for fast secure-boot

Apparatus and method for resisting side-channel attacks on cryptographic engines are described herein. An apparatus embodiment includes a cryptographic block coupled to a non-linear low-dropout voltage regulator (NL-LDO). The NL-LDO includes a scalable power train to provide a variable load current to the cryptographic block, randomization circuitry to generate randomized values for setting a plurality of parameters, and a controller to adjust the variable load current provided to the cryptographic block based on the parameters and the current voltage of the cryptographic block. The controller to cause a decrease in the variable load current when the current voltage is above a high voltage threshold, an increase in the variable load current when the current voltage is below a low voltage threshold; and a maximization of the variable load current when the current voltage is below an undervoltage threshold. The cryptographic block may be implemented with arithmetic transformations.

Time and frequency domain side-channel leakage suppression using integrated voltage regulator cascaded with runtime crypto arithmetic transformations

In one example an apparatus comprises a computer readable memory, an XMSS operations logic to manage XMSS functions, a chain function controller to manage chain function algorithms, a secure hash algorithm-2 (SHA2) accelerator, a secure hash algorithm-3 (SHA3) accelerator, and a register bank shared between the SHA2 accelerator and the SHA3 accelerator. Other examples may be described.

Combined SHA2 and SHA3 based XMSS hardware accelerator

In one example an apparatus comprises a computer readable memory, hash logic to generate a message hash value based on an input message, signature logic to generate a signature to be transmitted in association with the message, the signature logic to apply a hash-based signature scheme to a private key to generate the signature comprising a public key, and accelerator logic to pre-compute at least one set of inputs to the signature logic. Other examples may be described.

Accelerators for post-quantum cryptography secure hash-based signing and verification

In one example an apparatus comprises a computer-readable memory, signature logic to compute a message hash of an input message using a secure hash algorithm, process the message hash to generate an array of secret key components for the input message, apply a hash chain function to the array of secret key components to generate an array of signature components, the hash chain function comprising a series of even-index hash chains and a series of odd-index hash chains, wherein the even-index hash chains and the odd-index hash chains generate a plurality of intermediate node values and a one-time public key component between the secret key components and the signature components and store at least some of the intermediate node values in the computer-readable memory for use in one or more subsequent signature operations. Other examples may be described.

Odd index precomputation for authentication path computation

A method comprises generating, during an enrollment process conducted in a controlled environment, a dark bit mask comprising a plurality of state information values derived from a plurality of entropy sources at a plurality of operating conditions for an electronic device, and using at least a portion of the plurality of state information values to generate a set of challenge-response pairs for use in an authentication process for the electronic device.

Secure PUF-based device authentication using adversarial challenge selection

In one example an apparatus comprises a computer readable memory, a signature logic to generate a signature to be transmitted in association with a message, the signature logic to apply a hash-based signature scheme to the message using a private key to generate the signature comprising a public key, or a verification logic to verify a signature received in association with the message, the verification logic to apply the hash-based signature scheme to verify the signature using the public key, and an accelerator logic to apply a structured order to at least one set of inputs to the hash-based signature scheme. Other examples may be described.

Message index aware multi-hash accelerator for post quantum cryptography secure hash-based signing and verification

One embodiment provides a graphics processor comprising a memory controller and a graphics processing resource coupled with the memory controller. The graphics processing resource includes circuitry configured to execute an instruction to perform a matrix operation on first input including weight data and second input including input activation data, generate intermediate data based on a result of the matrix operation, quantize the intermediate data to a floating-point format determined based on a statistical distribution of first output data, and output, as second output data, quantized intermediate data in a determined floating-point format.

An integrated circuit features technology for generating a keystream. The integrated circuit comprises a cipher block with a linear feedback shift register (LFSR) and a finite state machine (FSM). The LFSR and the FSM are configured to generate a stream of keys, based on an initialization value and an initialization key. The FSM comprises an Sbox that is configured to use a multiplicative mask to mask data that is processed by the Sbox when the LFSR and the FSM are generating the stream of keys. Other embodiments are described and claimed.

Technology for generating a keystream while combatting side-channel attacks

Growing community of inventors

Hillsboro, OR, United States of America

Sanu K Mathew