Xilinx, Inc.

Actel Corporation, Inc.

Advanced Micro Devices Corporation

Other

Spansion Llc.

Santosh Yachareni

Kumar Rahul

Shidong Zhou

Anil Kumar Kandala

Narendra Kumar Pulipati

Sree Rkc Saraswatula

Vijay Kumar Koganti

Sandeep Vundavalli

Zhigang Wang

John J Wuu

Fethi Dhaoui

Kazuhiro Kurihara

Pau-Ling Chen

Brian C Gaide

Ming-Huei Shieh

Sundeep Ram Gopal Agarwal

Jing Jing Chen

Sree R K C Saraswatula

Golla V S R K Prasad

Udaya Kumar Bobbili

Teja Masina

Sree Rama Krishna Chaithnya Saraswatula

Steven P Young

Gregory William Bakker

Volker Hecht

Weiguang Lu

Nui Chong

Philip D Costello

James D Wesselkamper

Vidyadhara Bellippady

Pierre Maillard

Subodh Kumar

Fu-Hing Ho

Robert I Fu

Koushik De

Hsiao H Chen

Cheang Whang Chang

Vikram Santurkar

Michael Tsivyan

Mahendrakumar Gunasekaran

Srinivasa L Karumajji

Md Nadeem Iqbal

Vidyahara Bellippady

Vishwak R Manda

Amarnath Perla

Abhimanyu Kumar

Sri Deepti Pisipati

Jitendra Kumar Yadav

Sourabh Sharma

Sourabh Swarnkar

Mohammad Anees

Lakshmi Venkata Satya Lalitha Indumathi Janaswamy

Suresh Babu Kotha

Mrinmoy Goswami

Tabrez Alam

Md Hussain

Sanat Kumar Dubey

Gokul Puthenpurayil Ravindran

Embodiments herein describe a circuit for detecting a single event upset (SEU). The circuit includes a latch including an output node, a first parity node, and a second parity node and correction circuitry configured to correct a single event upset (SEU) at the output node using the first and second parity nodes.

System and method for SEU detection and correction

An integrated circuit (IC) device includes an error correction code (ECC) encoder circuitry configured to receive input data, determine min-terms in a Hamming matrix (H-Matrix) corresponding to the input data, and generate ECC data based on the min-terms and an output codeword based on the ECC data, and an error correction circuitry configured to generate a corrected output codeword based on the output codeword.

ECC optimization

An integrated circuitry (IC) device for a memory device includes driver circuitry, selection circuitry, clock generation circuitry, and self-time path circuitry. The driver circuitry generates a plurality of driver circuitry outputs. The selection circuitry selects one of the plurality of driver circuitry outputs based on a plurality of enable signals. The clock generation circuitry receives the selected one of the plurality of driver circuitry outputs from the selection circuitry, and generates a clock signal based on at least the selected one of the plurality of driver circuitry outputs from the selection circuitry. The self-time path circuitry of a memory receives the clock signal and generates a reset signal based on the clock signal. The plurality of driver circuitry outputs and the clock signal are based on the reset signal, and the self-time path circuitry corresponds to one or more columns of a memory bank.

Single port memory with multiple memory operations per clock cycle

A cascaded thin-oxide N-Well voltage steering circuit includes a reference voltage generator that outputs a reference voltage within a range of first and second supply voltages, a first voltage steering circuit that outputs a higher available one of the reference voltage and the second supply voltage as an interim voltage, and a second voltage steering circuit that outputs a higher available one of the first voltage and the interim voltage at an output of the second voltage steering circuit. The interim voltage is applied to N-wells of PMOS transistors of the first voltage steering circuit. The output of the second voltage steering circuit is applied to N-wells of PMOS transistors of the second voltage steering circuit. The output of the second voltage steering circuit may also be applied to N-wells of PMOS transistors of other circuitry. The cascaded thin-oxide N-Well voltage steering circuit may consist substantially of thin-oxide PMOS transistors.

Cascaded reference based thin-oxide only N-well steering circuit for contention solution in multi-supply designs

A memory device is disclosed herein that leverages high ratio column MUXES to improve SEU resistance. The memory device may be utilized in an integrated circuit die and chip packages having the same. In one example, as semiconductor memory device is provided that includes first and second arrays of semiconductor memory cells, a plurality of sense amplifiers configured to read data states from the first and second arrays of memory cells, and a first plurality of high ratio MUXES connecting the first and second arrays of memory cells to the plurality of sense amplifiers.

Single event upset tolerant memory device

Detection circuitry for an integrated circuit (IC) includes voltage divider circuitry, comparison circuitry, and calibration circuitry. The voltage divider circuitry receives a power supply signal and output a first reference voltage signal and a supply voltage signal based on the power supply signal. The comparison circuitry compares the first reference voltage signal and the supply voltage signal to generate an output signal. The calibration circuitry alters one or more parameters of the voltage divider circuitry to increase a voltage value of the supply voltage signal based on the comparison of the first reference voltage signal with the supply voltage signal.

Reference less glitch detection circuitry with autocalibration

Some examples described herein relate to multi-chip devices. In an example, a multi-chip device includes first and second chips. The first chip includes a power supply circuit and a logic circuit. The first and second chips are coupled together. The second chip is configured to receive power from the power supply circuit. The second chip includes a programmable circuit, a pull-up circuit, and a detector circuit. The detector circuit is configured to detect a presence of a power voltage on the second chip and responsively output a presence signal. The power voltage on the second chip is based on the power from the power supply circuit. The logic circuit is configured to generate a pull-up signal based on the presence signal. The pull-up circuit is configured to receive the pull-up signal and configured to pull up a voltage of a node of the programmable circuit responsive to the pull-up signal.

Multi-chip devices

Examples described herein generally relate to multi-chip devices having stacked chips. In an example, a multi-chip device includes a chip stack that includes chips. One or more chips each includes a selection circuit and a broken via pillar that includes first and second continuous portions. The first continuous portion includes a through substrate via and a first metal line. The second continuous portion includes a second metal line. The first and second metal lines are disposed within dielectric layers disposed on a side of the semiconductor substrate of the respective chip. The first and second continuous portions are aligned in a direction normal to the side of the semiconductor substrate. An input node of the selection circuit is connected to one of the first or second metal line. An output node of the selection circuit is connected to the other of the first or second metal line.

Multi-chip stacked devices

A device includes an amplifier, a plurality of selector circuitries, and a plurality of fabric dies. The amplifier is configured to output a supply power signal. Each selector circuitry of the plurality of selector circuitries receives the supply power signal from the amplifier. Each fabric die of the plurality of fabric dies has a corresponding selector circuitry of the plurality of selector circuitries. Each selector circuitry corresponding to a die of the plurality of dies is configured to provide the supply power signal received from the amplifier to its corresponding die responsive to a selection signal being asserted. Selector circuitries of the plurality of selector circuitries corresponding to unselected dies of the plurality of dies pull address supply power for the unselected dies to an input other than the supply power signal of the selector circuitries corresponding to the unselected die.

Low offset and enhanced write margin for stacked fabric dies

Examples described herein provide a method for disabling a defective portion of a fabric die of a stacked IC device. The method includes receiving a signal indicating that a portion of a fabric die of a stacked IC device including at least two fabric dies is defective. The method further includes, in response to the signal, pulling a source voltage rail of the defective portion to ground, thereby disabling the portion, and operating the remainder of the fabric die without interference from or contention with the disabled portion. In one example, the stacked IC device is an active on active (AoA) device, and the portion of the fabric die includes a configuration memory cell. In one example, the signal is received after power-up of the stacked IC device.

Yield-centric power gated regulated supply design with programmable leakers

Examples described herein generally relate to multi-chip devices having stacked chips. In an example, a multi-chip device includes a chip stack that includes chips. Neighboring chips are connected to each other. Plural chips of the chips collectively include columns of broken via pillars and bridges. Each of the plural chips has a broken via pillar in each column. The broken via pillar has first and second continuous via pillar portions aligned in a direction normal to a side of a semiconductor substrate of the respective chip. The first continuous via pillar portion is not connected within the broken via pillar to the second continuous via pillar portion. Each of the plural chips has one or more of the bridges. Each bridge connects, within the respective chip, the first continuous via pillar portion in a column and the second continuous via pillar portion in another column.

A circuit includes a master latch circuit and a slave latch circuit. The master latch circuit is configured to receive an input data signal associated with an input data voltage domain and generate a first output data signal associated with an output data voltage domain different from the input data voltage domain. The slave latch circuit is configured to receive, from the master latch circuit, the first output data signal and generate a second output data associated with the output data voltage domain.

Method and apparatus for multi-voltage domain sequential elements

Examples described herein generally relate to multi-chip devices having stacked chips. In an example, a multi-chip device includes a chip stack including a base chip and two or more overlying chips overlying the base chip. Neighboring chips of the chip stack are connected to each other. The chip stack includes identification generation connections and circuits configured to generate a unique identification of each overlying chip based on a relative position of the respective overlying chip with reference to the base chip. The chip stack includes a communication channel from the base chip to each overlying chip. Each overlying chip includes comparison and enable/disable logic (CEDL) communicatively coupled to the communication channel. The CEDL is configured to compare a target identification of data received by the respective overlying chip to the unique identification of the respective overlying chip and responsively enable or disable a recipient circuit of the respective overlying chip.

An integrated circuit (IC) includes an encoder circuit configured to receive input data including a plurality of data bits. A plurality of parity computation equations for a single error correct double error detect adjacent double error correct adjacent triple error detect (SECDEDADECADTED) Hamming code is received. A plurality of parity bits are computed using the plurality of parity computation equations. Write data including the data bits and the parity bits are provided to a write circuit. The write circuit writes the write data to a memory.

Method and apparatus for error detection and correction

An apparatus includes an encoder circuit block configured to receive input data. The encoder circuit block is configured to generate a plurality of parity bits from the input data and order the input data and the plurality of parity bits to generate encoded data. The encoder circuit block is configured to generate each of the plurality of parity bits based upon selected bits of the input data and orders the input data and the plurality of parity bits so that a decoder circuit block configured to decode the encoded data is able to perform operations including, at least in part, detecting a no bit error, detecting and correcting a single bit error, detecting a double bit error, detecting and correcting an adjacent double bit error, and detecting an adjacent triple bit error. The operations are independent of a number of memory banks used to store the encoded data. The decoder circuit block may also correct an adjacent triple bit error.

Encoding and decoding information for detecting and correcting bit errors

Growing community of inventors

Hyderabad Telangana, India

Santosh Yachareni