Navitas Semiconductor Limited

Globalfoundries U.S. Inc.

Newport Fab, LLC

Santosh Sharma

Daniel Marvin Kinzer

Ju Jason Zhang

Thomas J Ribarich

Marco Giandalia

Victor Sinow

Johnatan A Kantarovsky

Ren Huei Tzeng

Steven J Bentley

Michael Joseph Zierak

Hongwei Jia

Matthew Anthony Topp

Mei Yu Soh

Rajendran Krishnasamy

Edward J Preisler

Ephrem G Gebreselasie

Matteo Uccelli

Pil Sung Park

Maher J Hamdan

Jung Hee Lee

Embodiments of the present disclosure provide a semiconductor device, including: a high electron mobility transistor (HEMT) bidirectional switch including: a first source at a first potential; a second source at a second potential different than the first potential; and a substrate; and a biasing circuit, coupled to the first source of the bidirectional switch and the second source of the bidirectional switch, for biasing the substrate at a potential equal to the lower of the first potential of the first source of the bidirectional switch and the second potential of the second source of the bidirectional switch.

Substrate biasing for bidirectional high electron mobility transistor device

Monolithic high side GaN-based circuits using capacitors for level shifting. In one aspect, a power converter includes a GaN-based die, a switch formed on the GaN-based die and having a gate terminal, where the switch is arranged to be selectively conductive according to a driver signal applied to the gate terminal, a buffer circuit formed on the GaN-based die and arranged to receive an input signal and generate a corresponding differential output signal at a first output terminal and at a second output terminal, and a voltage level converter formed on the GaN-based die and having a first input terminal coupled to the first output terminal via a first capacitor and having a second input terminal coupled to the second output terminal via a second capacitor, where the first and second capacitors are formed on the GaN-based die, and the voltage level converter is arranged to generate the driver signal.

Monolithic high side gallium nitride device with integrated capacitive level shifter circuits

Systems and methods for a GaN-based motor drive circuit using synchronous rectification is disclosed. In one aspect, a method of operating a motor drive circuit includes providing a half-bridge circuit including a high-side GaN switch and a low-side GaN switch coupled in series at an output node, providing a motor coupled to the output node, turning on the high-side GaN switch such that a first current flows through the motor, turning off the high-side GaN switch, turning on the low-side GaN switch when a voltage at the output node drops below a predetermined threshold voltage, sensing, using a sense device coupled to the low-side GaN switch, a magnitude of a second current that flows through the low-side GaN switch, and turning off the low-side GaN switch when the magnitude of the second current drops below a predetermined threshold current.

System and methods for motor drive using GAN synchronous rectification

Circuits and methods that control a rate of change of a drain voltage as a function of time in a transistor are disclosed. In one aspect, the circuit includes a transistor having a gate terminal that controls operation of the transistor, and a control circuit coupled to the gate terminal and arranged to change a voltage at the gate terminal at a first rate of voltage with respect to time from a first voltage to a first intermediate voltage, and further arranged to change the voltage at the gate terminal at a second rate of voltage with respect to time from the first intermediate voltage to a second intermediate voltage, where the first rate is different than the second rate.

Transistor DV/DT control circuit

Embodiments of the disclosure provide an electrically programmable fuse (efuse) over crystalline semiconductor material. A structure according to the disclosure includes a plurality of crystalline semiconductor layers. Each crystalline semiconductor layer includes a compound material. A metallic layer is on the plurality of crystalline semiconductor layers. The metallic layer has a lower resistivity than an uppermost layer of the plurality of crystalline semiconductor layers. A pair of gate conductors is on respective portions of the metallic layer. The metallic layer defines an electrically programmable fuse (efuse) link between the gate conductors.

Electrically programmable fuse over crystalline semiconductor materials

A structure includes a negative temperature coefficient (NTC) resistor for use in gallium nitride (GaN) technology. The NTC resistor includes a p-type doped GaN (pGaN) layer, and a gallium nitride (GaN) heterojunction structure under the pGaN layer. The GaN heterojunction structure includes a barrier layer and a channel layer. An isolation region extends across an interface of the barrier layer and the channel layer, and a first metal electrode is on the pGaN layer spaced from a second metal electrode on the pGaN layer. The NTC resistor can be used as a temperature compensated reference in a structure providing a temperature detection circuit. The temperature detection circuit includes an enhancement mode HEMT sharing parts with the NTC resistor and includes temperature independent current sources including depletion mode HEMTs.

Temperature detection using negative temperature coefficient resistor in GaN setting

An electronic device includes a semiconductor substrate and a bidirectional transistor switch formed on the substrate, the bidirectional switch including a first source node, a second source node and a common drain node. A first transistor is formed on the substrate and includes a first source terminal, a first drain terminal and a first gate terminal, wherein the first source terminal is connected to the substrate, the first drain terminal is connected to the first source node and the first gate terminal is connected to the second source node. A second transistor is formed on the substrate and includes a second source terminal, a second drain terminal and a second gate terminal, wherein the second source terminal is connected to the substrate, the second drain terminal is connected to the second source node and the second gate terminal is connected to the first source node.

Circuits and methods for controlling a voltage of a semiconductor substrate

Disclosed are protective structures using depletion-mode and enhancement-mode transistors. A structure according to the disclosure may include a depletion-mode transistor having a gate coupled to ground and a first source/drain terminal. An enhancement-mode transistor includes a gate coupled to a second source/drain terminal of the depletion-mode transistor and a first source/drain terminal coupled to the gate of the depletion-mode transistor. The depletion-mode transistor limits a current flow from the first source/drain terminal to the gate of the enhancement-mode transistor.

Protective structure with depletion-mode and enhancement-mode transistors

A GaN logic circuit may include an input node receiving an input voltage, a first pull up transistor pulling up an output voltage in response to the input voltage, and a first depletion mode transistor having a first gate to which a first gate voltage is applied and a second gate to which a second gate voltage is applied. The first depletion mode transistor may control the first pull up transistor in response to a gate voltage difference between the first gate voltage and the second gate voltage. The logic device may further include a capacitor having a first end coupled to the first depletion mode transistor and a second end coupled to the first pull up transistor.

Charge pumps, logic circuits including charge pumps, logic devices including logic circuits, and methods of operating logic circuits

A circuit structure includes an enhancement mode transistor and a turn-off slew rate controller for automatically adding drain-source capacitance to the transistor when the transistor is transitioning to an off state. The added drain-source capacitance slows the turn-off slew rate (dV/dt_off) of the transistor without also increasing the turn-off energy loss (E_off). The slew rate controller can include: sensors connected to the drain region for sensing both the drain voltage and the slew rate, respectively; a logic circuit for generating and outputting an enable signal based on output voltages from the sensors; and a capacitance adder for adding to the drain-source capacitance only when the logic value of the enable signal indicates that the drain voltage is at or above a predetermined positive drain voltage level and the slew rate is positive.

Transistor with integrated turn-off slew rate control

An integrated circuit (IC) having a high voltage semiconductor device with a plurality of field plates between the gate and drain. The IC further includes a biasing circuit electrically coupled to each of the plurality of field plates, the biasing circuit including a plurality of high voltage depletion mode transistors, each having a pinch off voltage. The high voltage depletion mode transistors may have different pinch off voltages, and each of the field plates are each independently biased by a different one of the high voltage depletion mode transistors.

High voltage device with linearizing field plate configuration

Disclosed are circuits for controlling slew rate of a transistor during switching. Each circuit includes a first transistor (e.g., a gallium nitride (GaN)-based high electron mobility transistor (HEMT) or metal-insulator-semiconductor HEMT (MISHEMT)), a capacitor, and a second transistor. The first transistor includes a first gate connected to a pad for receiving a pulse-width modulation (PWM) signal, a first drain region connected to a first plate of the capacitor, and a first source region. The second transistor includes a second gate connected to a second plate of the capacitor, a second drain region, and a second source region and is connected to both the pad and the first transistor. The connection between the first and second transistors varies depending on whether the first transistor is an enhancement or depletion mode device and on whether the slew rate control is employed for on state or off state switching.

Circuit for controlling the slew rate of a transistor

A driver circuit is disclosed. The driver circuit is configured to generate a drive voltage for driving a bootstrap transistor. The driver circuit includes an input node and an output node, a first circuit including a plurality of switches, a first capacitor and a second capacitor, and a pass gate switch coupled between the output node and the first capacitor. In one aspect, the first circuit, the first and second capacitors and the pass gate switch are arranged to cause an output voltage at the output node to change from a first output voltage to a second output voltage. In another aspect, a resistor is connected between the first capacitor and the second capacitor, and a feedback switch is connected in parallel to the resistor. The feedback switch is turned on in response to a feedback signal, thereby reducing an impedance value of the resistor.

Driver circuits for gallium nitride half bridge power converters

The present disclosure relates to a circuit and, more particularly, to comparator circuits used with a depletion mode device and methods of operation. The circuit includes: a comparator; a transistor connected to an output of the comparator; and a depletion mode device connected to ground and comprising a control gate connected to the transistor.

Growing community of inventors

Laguna Niguel, CA, United States of America

Santosh Sharma