Lucent Technologies Inc.

Santosh K Misra

Ravi Kumar Kolagotla

Jiancheng Mo

Hosahalli R Srinivas

An unsigned integer comparator for use when comparing an n-bit received signal (such as an address) with an n-bit known signal ('comparison address'). The first stage of the comparator may be configured in advance, since the values of both a 'comparison signal' and a 'select signal' are known a priori. When the 'current signal' arrives, the bits of this signal are then compared against the associated bits of the comparison signal. Subsequent stages of the comparator perform comparison operations of increasing length, dependent upon the outcome of the previous stage (i.e., a first set of 2-bit comparisons, then 4-bit, 8-bit, etc.), until the entire n-bit integers are ultimately compared and a final output is generated.

Unsigned integer comparator

An integrated circuit includes an n-bit counter having a plurality of k subcounters where both n and k are integers. At least one of the subcounters includes a switchable device adapted to receive a carry-out signal from an adjacent subcounter as a first input, a test carry signal as a second input, and a control input, the switchable device being capable of providing one of its inputs as an output, the control input capable of controlling selection of the output which is a carry signal. The subcounter also includes an n/k-bit counter, the n/k-bit counter receiving the carry signal and providing n/k output bits, and logic for combining the n/k-bits output from the n/k bit counter with the carry-out signal from an adjacent subcounter to provide an output that is a carry-out signal from the subcounter. The logic introducing a single gate delay between the carry-out signal from the adjacent subcounter and the carry-out signal from the subcounter.

High-speed binary synchronous counter

An N-bit binary synchronous counter includes K counter stages, with each stage including N/K flip-flops or other suitable storage elements. A given one of the counter stages receives a carry-in signal generated by another counter stage or by a carry logic circuit. The given counter stage includes a selection circuit for selecting one of two precomputed values for application to an input of a storage element in that stage based on a value of the carry-in signal. The selection circuit may include a two-input multiplexer for each of the N/K storage elements of the given counter stage. The jth multiplexer includes a first input coupled to an output of the jth storage element, and a second input coupled to an output of a logic circuit. The logic circuit generates a logic function based on the output of the jth storage element and other lower significant storage elements in the stage. The carry-in signal is applied as a select signal to the multiplexer and is used to select which of the two multiplexer inputs will be applied as the data input of the storage element. This selection of one of two precomputed values for application to a storage element input results in the counter having a critical path delay which is substantially independent of N.

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Allentown, PA, United States of America

Santosh K Misra