Digital Equipment Corporation

Santosh K Hasani

Satish L Rege

Mark F Kempf

Ramesh S Kalkunte

A parser for reading bits of a packet has a set of logic circuits implemented in a computer chip; a memory interacting with the computer chip, the memory providing first data to the set of logic circuits; means for reading bits from any field of packet into the set of logic circuits, the bits providing second data to the set of logic circuits; means, responsive to the first data and the second data, for the logic circuits to interpret bits of the packet.

Real time parser for data packets in a communications network

A monitor for packets on a local area network includes a set of logic circuits implemented in a computer chip, a memory interacting with the computer chip to provide monitoring data to the logic circuits, logic for receiving a packet from the local area network, and a parser to process bits of the packet as they are received, wherein the parser uses the monitoring data in conjunction with the received bits to provide forwarding data which indicates the type of packet received. The monitor uses the forwarding data to determine whether the received packet is stored in memory, discarded, or forwarded to other host computers in the network. The monitor uses type information from the forwarding data to maintain count information of the different types of packets which may be forwarded to a host computer or a remote monitoring device.

Growing community of inventors

Nashua, NH, United States of America

Santosh K Hasani