Cirrus Logic Inc.

Cirrus Logic International Semiconductor Limited

Santosh Astgimath

John Laurence Pennock

Jean Pierre Lasseuguette

Circuitry for biasing a MEMS transducer and associated signal processing circuitry. A reference voltage generator is configured to generate a reference voltage at a reference voltage node. Control circuitry generates a drive signal to control a first current source which is operable to supply a current to the reference voltage generator in response to the drive signal. A switched DC-DC converter, such as a charge pump has a voltage input connected to the reference voltage node and a voltage output for providing a bias voltage for the MEMS transducer. The DC-DC converter cyclically switches in a sequence of states including at least a first state where a first converter capacitance is disconnected from the voltage input followed by a second state where the first converter capacitance is connected to the voltage input. A second current source is operable to supply a bias current in response to a voltage at a bias control node. Switch control circuitry is configured to cyclically open and close a switch connected between the drive node and the bias control node, such that the switch is open during a time window that includes the time at which the switched DC-DC converter switches from the first state to the second state.

Biasing circuitry for MEMS transducers

This application relates to amplifier circuitry for amplifying a signal from a MEMS transducer. A super source follower circuit () is provided which includes a feedback path from its output node (N) to a control bias node (BC) in order to provide a preamplifier signal gain that may be greater than unity. A first transistor (M) is configured to have its gate node connected to an input node (N) for receiving the input signal (V) and its drain node connected to an input node (X) of an output stage (A). The source node of the first transistor is connected to the output node (N). A current source (I) is configured to deliver a current to the drain node of the first transistor (M), wherein the current source (I) is controlled by a bias control voltage (V) at the bias control node (BC). A feedback impedance network (Z) comprising a first port connected to the output node (N) and a second port connected to the bias control node (BC) is provided.

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Edinburgh, United Kingdom

Santosh Astgimath