Stmicroelectronics S.r.l.

Stmicroelectronics (rousset) Sas

Santi Carlo Adamo

Liliana Arcidiacono

Francesco Pirozzi

Agatino Antonino Alessandro

Francesco Bombaci

Rosalino Critelli

Ignazio Cala'

Giuliana Demilato

Ignazio Cala′

Vincent Onde

Gaetano Di Stefano

Santi Nunzio Antonino Pagano

Salvatore Pantano

Ugo Mari

Edmondo Gangi

Orazio Musumeci

Fabrizio Meli

Martino Quattrocchi

Gianluca Vincenzo Aureliano

A processing system comprising a first sub-circuit configured to be powered by a first supply voltage and a second sub-circuit configured to be powered by a second supply voltage. The first sub-circuit comprises a general-purpose input/output register. The second sub-circuit comprises: a storage circuit configured to selectively store configuration data from the general-purpose input/output register; an input/output interface, at least one peripheral and a selection circuits to exchange signals of the peripherals, and the stored configuration data with the input/output interface. A power management circuit is configured to manage a normal operating mode, and a low-power mode during which the configuration data are maintained stored and the first sub-circuit is switched off. The power management circuit activates the low-power mode in response to receiving a commands, and resumes the normal operating mode in response to a wake-up events.

Processing system, related integrated circuit and method

A processing system comprising a first sub-circuit configured to be powered by a first supply voltage and a second sub-circuit configured to be powered by a second supply voltage. The first sub-circuit comprises a general-purpose input/out register. The second sub-circuit comprises: a storage circuit configured to selectively store configuration data from the general-purpose input/out register; an input/output interface, at least one peripheral and a selection circuits to exchange signals of the peripherals, and the stored configuration data with the input/output interface. A power management circuit is configured to manage a normal operating mode, and a low-power mode during which the configuration data are maintained stored and the first sub-circuit is switched off. The power management circuit activates the low-power mode in response to receiving a command, and resumes the normal operating mode in response to a wake-up event.

In an embodiment, a system includes a slave circuit configured to receive an external clock signal from a master circuit, the slave circuit comprising first and second peripherals configured to receive respective clock signals obtained from the external clock signal, wherein the master circuit is configured to send to the slave circuit the external clock signal according to two different timing modes, wherein the slave circuit comprises a logic circuit configured to provide a locking signal to the first peripheral circuit when the logic circuit detects a given operating mode of the slave circuit, wherein the master circuit is configured to send the external clock signal according to a first timing mode before receipt of the locking signal, and wherein the master circuit is configured, following upon receipt of the locking signal, to send the external clock signal according to a second timing mode different from the first timing mode.

Circuit arrangement with clock sharing, and corresponding method

A circuit includes a set of LED driver devices and a controller including a set of nodes coupled to a first slave address pin and a second slave address pin in each LED driver devices in the set of LED driver devices. Each LED driver device includes a finite state machine (FSM) configured to generate LED drive PWM-modulated signal patterns, an oscillator configured to generate a clock signal for the FSM, a first signal path activatable between the first slave address pin and the FSM, and a second signal path activatable between the FSM and the second slave address pin.

LED driver circuit, corresponding device and method

A circuit includes a set of LED driver devices and a controller including a set of nodes coupled to a first slave address pin and a second slave address pin in each LED driver devices in the set of LED driver devices. Each LED driver device includes: a finite state machine (FSM) configured to generate LED drive PWM-modulated signal patterns; an oscillator configured to generate a clock signal for the FSM; a first signal path activatable between the first slave address pin and the FSM; and a second signal path activatable between the FSM and the second slave address pin.

A circuit includes: a communication interface configured to receive data; a plurality of output terminals; a bank of input registers coupled to the communication interface; a bank of buffer registers; a bank of output registers; a signal generator configured to generate a plurality of output signals based on respective registers of the bank of output registers at respective output terminals; and a conversion stage configured to: when data is received by the bank of input registers from the communication interface, sequentially convert content of the input registers of the bank of input registers and store the converted content into corresponding buffer registers of the bank of buffer registers based on a conversion function, and when the conversion stage finishes storing the converted content into the buffer registers, simultaneously copy content from the buffer registers into corresponding output registers of the bank of output registers.

Pipelined exponential law brightness conversion for a multi-channel LED driver

A circuit includes: a plurality of memory locations configured to store pulse width modulation (PWM) signal generation data, the memory locations being arranged in N sets of memory locations, each including i channel memory locations, each channel memory location being configured to store a respective duty-cycle value for a respective one of N PWM modulation patterns; a selection circuit configured to selectively access a selected set of the sets of memory locations; a buffer circuit configured to store the PWM signal generation data from the channel memory locations of the selected set; and a finite state machine configured to receive PWM signal generation input data indicative of a plurality of PWM modulation patterns with a respective plurality of duty-cycle values, the finite state machine configured to activate the selection circuit to load the PWM signal generation data from the channel memory locations of the selected set to the buffer circuit.

Pulse width modulation pattern generator circuit, corresponding device and method

A battery charger which includes an input supply terminal configured to receive a supply signal, a battery terminal configured to be connected to a battery, at least one output terminal and an electrical path between the battery terminal and the output terminal, at least one device for the detection of one alarm condition of the battery or the battery charger. The battery charger includes circuitry configured to enable the at least one detection device at timing intervals when the battery supplies the at least one output terminal.

Battery charger

A battery charger includes an input supply terminal configured to receive a supply signal, a battery terminal configured to be connected to a battery and at least one output terminal, a switch arranged in the electrical path between the battery terminal and at least one output terminal, an element configured to store an information representative of an alarm condition of the battery and to open the switch when the alarm condition occurs, with the supply signal being absent and the battery supplying the at least one output terminal, and to close the switch when the supply signal is received at the input supply terminal.

Battery charger for providing battery protection from over discharge from voltage or current and shipping mode

An analog-digital converter for converting an analog signal into a digital signal includes a first configuration register for configuring a first group of channels and a second configuration register for configuring a second group of channels. The conversion result of the channels of the first group is transferred to a memory via a direct memory access. Each channel of the second group of channels has an associated respective data register and the conversion results of the channels of the second group are stored in the respective data registers.

Analog-digital converter and corresponding system and method

An embodiment of a circuit switches between at least a first clock signal and a second clock signal in response to a corresponding switch command, and includes a selection module to select at a switch instant said second clock signal under the control of a signal selector. The circuit comprises a logic-based filter module located downstream of said selection module and configured to produce an outgoing clock signal filtered under the control of a filter signal and also includes a control module configured to receive said switch command and to send said select signal to said selection module delaying said switch instant by a first interval of time, said control module also being configured to send said active filter signal to said filter module in a second interval of time that comprises an edge of the first clock signal and an edge of the second clock signal.

Circuit to switch between clock signals and related method

A system for reducing power consumption in processing apparatus including a memory comprises a clock controller for controlling the clock period of the processing apparatus to switch the processing apparatus to a slow operating mode wherein the clock period is longer then the time required to recover from memory standby mode plus the time to execute a read command in the memory. A memory management module is provided configured for controlling the status of the memory during the slow operating mode by:

Method and system for power consumption management, and corresponding computer program product

A system for configuring registers of microcontrollers includes first register and second registers. The system includes a data source for loading a datum into the first register and the logic complement of said datum in the second register. The system also includes a comparator which verifies the identity between the datum in the first register and the logic complement in the second register, and, where the identity is not verified, generates a signal indicating that the data have been corrupted by a disturbance. The system also includes a final-state machine which disables the comparator during writing of the registers.

Method and system for configuring registers in microcontrollers, and corresponding computer-program product

In order to manage, in the interrupt stage, a memory stack associated with a microcontroller according to a Program Counter signal and to a Condition Code Register signal that can be contained in respective registers, a first part of memory stack is provided which comprises a register for the Program Counter signal, and a second part of memory stack consisting of a bank of memory elements equal in number to the number of bits of the Condition Code Register signal for the number of the interrupts of the microcontroller. The two parts of stack are made to function in parallel by respective stack-pointer signals.

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Aci Castello, Italy

Santi Carlo Adamo