Qualcomm Incorporated

Nvidia Corporation

Santhosh Kumar Gude

Sunil Rao Sudhakaran

Eskinder Hailu

Arash Zargaran-Yazd

Seema Kumar

Hadi Goudarzi

Rajeev Sharma

Parth Patel

A system includes a transmitter to transmit a set of bits associated with signaling having one or more levels. The system includes a receiver coupled to the transmitter, the receiver to receive the set of bits and generate a first plurality of digital values, each digital value generated at a first timing value and a plurality of reference voltages, the reference voltage incremented based at least in part on generating a digital value of the first plurality of digital values. The receiver is to generate a second plurality of digital values at a second timing value and the plurality of reference voltages, the first timing value incremented to the second timing value based at least in part on generating the first plurality of digital values. The system includes a controller to determine an amplitude associated with each the first and second plurality of digital values.

On-chip virtual oscilloscope using high-speed receiver sampler readback

A desirable feature of a SERDES design is power savings. One way to achieve power savings is by keeping the CDR circuit OFF during most of the time when a link is active between a transmitter and a receiver. However, due to voltage supply noise, temperature fluctuations and uncorrelated crosstalk, the receiver data may shift and/or the eye may collapse if the CDR is not turned ON to take care of these modulations. To address such disadvantages, it is proposed to generate a CDR profile that can specify optimum CDR ON and OFF time so that link stability may be maintained while saving power.

Optimizing clock/data recovery power while maintaining link stability in source synchronous applications

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San Jose, CA, United States of America

Santhosh Kumar Gude