Micron Technology Incorporated

Intel Corporation

Santanu Sarkar

Farrell Martin Good

Stephen W Russell

Ahmed Nayaz Noemaun

Tao D Nguyen

Yongjun Jeff Hu

Adam William Saxler

Shu Qin

Andrea Gotti

Jay Steven Brown

Janos Fucsko

Jerome A Imonigie

Robert K Grubbs

Josiah Jebaraj Johnley Muthuraj

Kent H Zhuang

Benjamin E Greenwood

Some embodiments include an integrated assembly having a pair of substantially parallel features spaced from one another by an intervening space. A conductive pipe is between the features and substantially parallel to the features. The conductive pipe may be formed within a tube. The tube may be generated by depositing insulative material between the features in a manner which pinches off a top region of the insulative material to leave the tube as a void region under the pinched-off top region.

Methods of forming conductive pipes between neighboring features, and integrated assemblies having conductive pipes between neighboring features

Apparatus and methods related to forming films on sidewalls of memory cell stacks in memory and logic devices. In one approach, a silicon wafer is held in a chamber of an atomic layer deposition (ALD) reactor. A temperature in the reactor is controlled to a first temperature (e.g., room temperature or below) where a first gas reactant that is provided into the chamber condenses and is adsorbed on the target wafer or substrate. The first reactant or precursor is partly vaporized at a second temperature in the reactor that is greater than the first temperature. A second gas reactant is provided into the chamber. The second gas reactant reacts with the adsorbed portion of the first gas reactant in its activated state. The reaction product is a film on the sidewall of a memory cell stack or logic devices. The foregoing steps are repeated to form a desired thickness of the film.

Reactor to form films on sidewalls of memory cells

Some embodiments include an integrated assembly having a first graphene-containing-material offset from a second graphene-containing-material. The first graphene-containing-material includes a first graphene-layer-stack with first metal interspersed therein. The second graphene-containing-material includes a second graphene-layer-stack with second metal interspersed therein. A conductive interconnect couples the first and second graphene-containing materials to one another.

Integrated assemblies having graphene-containing-structures

In a variety of processes for forming electronic devices that use spin-on dielectric materials, properties of the spin-on dielectric materials can be enhanced by curing these materials using plasma doping. For example, hardness and Young's modulus can be increased for the cured material. Other properties may be enhanced. The plasma doping to cure the spin-on dielectric materials uses a mechanism that is a combination of plasma ion implant and high energy radiation associated with the species ionized. In addition, physical properties of the spin-on dielectric materials can be modified along a length of the spin-on dielectric materials by selection of an implant energy and dopant dose for the particular dopant used, corresponding to a selection variation with respect to length.

Plasma doping of gap fill materials

An electronic device comprising a stack structure comprising one or more stacks of materials and one or more silicon carbide materials adjacent to the one or more stacks of materials. The materials of the one or more stacks comprise a single chalcogenide material and one or more of a conductive carbon material, a conductive material, and a hardmask material. The one or more silicon carbide materials comprises silicon carbide, silicon carboxide, silicon carbonitride, silicon carboxynitride, and also comprise silicon-carbon covalent bonds. The one or more silicon carbide materials is configured as a liner or as a seal. Additional electronic devices are disclosed, as are related systems and methods of forming an electronic device.

Methods of forming electronic devices comprising silicon carbide materials

A memory cell design is disclosed. The memory cell structure includes phase change and selector layers stacked between top and bottom electrodes. An ohmic contact may be included between the phase change and selector layers. A multi-layer liner structure is provided on sidewalls of the phase change layer. In some such cases, the liner structure is above and not on sidewalls of the selector layer. The liner structure includes a first dielectric layer, and a second dielectric layer on the first dielectric layer. The liner structure includes a third dielectric layer on the second dielectric layer and that is sacrificial in nature, and may not be present in the final structure. The second dielectric layer comprises a high-k dielectric material or a metal silicate material. The second dielectric layer protects the phase change layer from lateral erosion and physical vertical etch and provides etch selectivity during the fabrication process.

Memory device with multi-layer liner structure

A new liner structure for improving memory cell design is disclosed that incorporates a boron nitride dielectric layer. An example memory device includes an array of memory cells with each of at least some of the memory cells having a stack of layers, the stack comprising at least one phase change layer. A dielectric layer is provisioned over one or more sidewalls of at least the phase change layer. The dielectric layer comprises both nitrogen and boron. The dielectric layer may be part of a liner structure that includes multiple layers, such as an alternating layer stack of boron nitride and silicon nitride. The dielectric layer can be deposited at low temperature (e.g., less than about 300&#xb0; C.) while maintaining a low hydrogen content and a relatively high thermal conductivity.

Memory device with boron nitride liner

An electronic device comprising a stack structure comprising one or more stacks of materials and a metal oxide material adjacent to the stacks of materials. The materials of the stacks comprise one or more chalcogenide materials. The metal oxide material comprises aluminum oxide, aluminum silicate, hafnium oxide, hafnium silicate, zirconium oxide, zirconium silicate, or a combination thereof and the metal oxide material extends continuously from an upper portion of the one or more stacks of materials to a lower portion of the one or more stacks of materials. Additional electronic devices are disclosed, as are related systems and methods of forming an electronic device.

Electronic devices comprising metal oxide materials and related methods and systems

Electronic devices comprising silicon carbide materials

Systems, apparatuses, and methods related to semiconductor structure formation are described. An example apparatus includes a structural material for a semiconductor device. The structural material includes an orthosilicate derived oligomer having a number of oxygen (O) atoms each chemically bonded to one of a corresponding number of silicon (Si) atoms and a chemical bond formed between an element from group 13 of a periodic table of elements (e.g., B, Al, Ga, In, and Tl) and the number of O atoms of the orthosilicate derived oligomer. The chemical bond crosslinks chains of the orthosilicate derived oligomer to increase mechanical strength of the structural material, relative to the structural material formed without the chemical bond to crosslink the chains, among other benefits described herein.

Growing community of inventors

Boise, ID, United States of America

Santanu Sarkar