Infineon Technologies LLC

Cypress Semiconductor Corporation

Santanu Kumar Samanta

Krishnaswamy Ramkumar

Ravindra Manohar Kapre

Long Hinh

Vineet Agrawal

Venkatraman Prabhakar

Swatilekha Saha

Michael Amundson

Venkataraman Prabhakar

A method of operating a semiconductor inference device that includes the steps of writing one of multiple analog weight values to memory cells of a non-volatile memory (NVM) array, receiving inputs through a bus system, performing multiply accumulate (MAC) operations based on the inputs and the stored analog weight values, converting results of the MAC operations to outputs, and transmitting the outputs through the bus system.

Silicon-oxide-nitride-oxide-silicon based multi-level non-volatile memory device and methods of operation thereof

A method of fabricating a multi-level memory cell that includes the steps of forming a shallow trench isolation (STI) in a substrate, performing clean and preclean process such that top surfaces of the STI and substrate are substantially leveled, forming a tunnel dielectric using a radical oxidation process, forming upper and lower silicon oxynitride layers in which an amount of electric charge trapped represents N&#xd7;analog values stored in the multi-level memory cell, N is a natural number greater than 2, forming a blocking dielectric and patterning to form a memory stack, and forming a lightly-doped drain extension (LDD) adjacent to the memory stack by angled implant such that the LDD extends at least partly under the memory stack.

Silicon-oxide-nitride-oxide-silicon multi-level non-volatile memory device and methods of fabrication thereof

A semiconductor inference device that has a non-volatile memory (NVM) array including NVM cells arranged in rows and columns, in which each NVM cell comprises a charge trapping transistor configured to store one of N&#xd7;analog values corresponding to N&#xd7;levels of its drain current (ID) or threshold voltage (VT) levels, representing N&#xd7;weight values for multiply accumulate (MAC) operations. The semiconductor inference device also includes digital-to-analog (DAC) function and multiplexor (mux) function configured to generate an analog MAC result based on the digital inputs converted results and the weight values read results, and analog-to-digital (ADC) function configured to convert the analog MAC result of the mux function to a digital value. Other embodiments of the semiconductor inference device and related methods and systems are also disclosed.

A semiconductor device that has a silicon-oxide-nitride-oxide-silicon (SONOS) based non-volatile memory (NVM) array including charge-trapping memory cells arranged in rows and columns and configured to store one of N&#xd7;analog values. Each charge-trapping memory cells may include a memory transistor including an angled lightly doped drain (LDD) implant extends at least partly under an oxide-nitride-oxide (ONO) layer of the memory transistor. The ONO layer disposed within the memory transistor and over an adjacent isolation structure has the same elevation substantially.

A semiconductor device that has a semiconductor-oxide-nitride-oxide-semiconductor (SONOS) based non-volatile memory (NVM) array including NVM cells arranged in rows and columns, in which NVM transistors of the NVM cells are configured to store N&#xd7;analog values corresponding to the N&#xd7;levels of their drain current (I) or threshold voltage (V) levels, digital-to-analog (DAC) function that receives and converts digital signals from external devices, column multiplexor (mux) function that is configured to select and combine the analog value read from the NVM cells, and analog-to-digital (ADC) function that is configured to convert analog results of the column mux function to digital values and output the digital values.

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West Bengal, India

Santanu Kumar Samanta