Intel Corporation

Other

Santanu Chaudhuri

Sanjay Dabral

Klaus J Ruff

Karthisha S Canagasaby

Pascal A Meier

Evelina F Yeung

Kuljit Singh Bains

Arvind A Kumar

James A McCall

Venkatraman Iyer

David Stewart Dunning

Theodore Zale Schoenborn

Darren S Jue

Naveen Cherukuri

Tim Frodsham

Joseph H Salmon

David N Shykind

Richard S Jensen

Dennis R Halicki

Arvind Kumar

A method, system and apparatus to self-determine equalization parameters for a channel. An initiator sends an equalization insensitive signal (EIS) to a responder on channel to be equalized and begins a count. A responder responds with an EIS. When the initiator receives the response EIS the count is terminated. The count, which constitutes a measure of delay in the channel, may be used to determine desirable equalization parameters for the channel.

Adaptive delay base loss equalization

A method and system to adapt communication links statically and/or dynamically to their individual link conditions on a platform. The communicatively coupled devices have logic to adapt one or more settings of a respective one or more communication links with another device based at least in part on a respective metric of received data patterns from the respective one or more communication links. The communicatively coupled devices in the platform have a back channel to allow feedback or information to be sent from one receiving device to a transmitting device in one embodiment of the invention.

Method and system of adapting communication links to link conditions on a platform

Link initialization techniques to decouple the read training from the write training. Read training may be accomplished in a robust manner before write training is performed. These techniques may provide significantly improved link initialization times. A user-programmable register within a dynamic random access memory (DRAM) module may be utilized by the decoupled read training and write training processes. The decoupling may result in shorter and more robust training segments that may support faster training and/or increased link speeds.

Memory link initialization

Described herein is a method and an apparatus for training a memory signal via an error signal of a memory. The method comprises transmitting from a memory controller a command-address (C/A) signal to a memory module; determining by the memory controller an error in the memory module via an error signal from an error pin of the memory module, the error associated with the C/A signal transmitted to the memory module; and modifying by the memory controller the C/A signal in response to determining an error in the memory module, wherein the error pin is a parity error pin of the memory module, and wherein the memory module comprises a Double Data Rate 4 (DDR4) interface.

Method and apparatus for training a memory signal via an error signal of a memory

Embodiments of a programmable passive equalizer are described herein.

Programmable passive equalizer

According to some embodiments an apparatus comprising a vote generator, a vote governor, and a local clock controller is provided. The vote generator generates votes based on a local clock signal and transitions in a stream of received data. The vote governor receives the generated votes and discards at least some of the votes. The local clock controller adjusts the local clock signal based on a generated vote that has not been discarded.

Local receive clock signal adjustment

A method and apparatus for retraining skew compensation in an interface is presented. In one embodiment, a retraining interval is determined, and counters in the transmitting agent and receiving agent count up until the retraining interval is reached. A tracking unit used to select one of several interpolated clocks may then be powered up, and a special retraining phit may be sent across the interface. During the retraining process, the transfer of flits into and out of the flow-control mechanism may be inhibited. When the retraining process is finished, the tracking unit may be powered down.

Method and apparatus for periodically retraining a serial links interface

According to some embodiments, a low gain phase-locked loop circuit is provided.

Low gain phase-locked loop circuit

A method for setting multiple chip parameters using one IC terminal is described. The chip comprises a first circuit coupled to the pin for setting a first parameter. A second circuit coupled to the pin sets a second parameter. In addition, a third circuit coupled to the pin sets a third parameter of the chip.

Setting multiple chip parameters using one IC terminal

A low gain phase-locked loop circuit comprising a phase detector, a plurality of voltage controlled oscillators, wherein each voltage controlled oscillator is selectable to provide an output clock signal based at least in part on information generated by the phase detector; and a multiplexer to output a signal generated by one of the voltage controlled oscillators as the output clock signal based on a multi-bit selection control signal.

Growing community of inventors

Mountain View, CA, United States of America

Santanu Chaudhuri