Fujitsu Corporation

Fujitsu Semiconductor Limited

Sanroku Tsukamoto

Hirotaka Tamura

Satoshi Matsubara

Toshiaki Endo

Ian Juso Dedic

Masaru Sawada

Takayuki Hamada

Takumi Danjo

Yanfei Chen

Hiroko Murakami

Kuniyoshi Kamei

Motomu Takatsu

Hisakatsu Yamaguchi

Takayuki Shibasaki

Suguru Tachibana

Koji Okada

Masaya Kibune

Kenta Aruga

Ali Sheikholeslami

Noboru Yoneoka

Masato Yoshioka

Jumpei Koyama

David Thach

Akihiko Ohwada

Kazuya Takemoto

Takeshi Takayama

Toshiyuki Miyazawa

Joshua Liang

Katsumi Andou

An optimization apparatus calculates a first portion, among energy change caused by change in value of a neuron of a neuron group, caused by influence of another neuron of the neuron group, determines whether to allow updating the value, based on a sum of the first and second portions of the energy change, and repeats a process of updating or maintaining the value according to the determination. An arithmetic processing apparatus calculates the second portion caused by influence of a neuron not belonging to the neuron group and an initial value of the sum. A control apparatus transmits data for calculating the second portion and the initial value to the arithmetic processing apparatus, and the initial value and data for calculating the first portion to the optimization apparatus, and receives the initial value from the arithmetic processing apparatus, and a value of the neuron group from the optimization apparatus.

Optimization system, optimization apparatus, and optimization system control method for solving optimization problems by a stochastic search

A problem is inputted into an operation unit. A computation unit searches for a ground state of an Ising model. A management unit converts the problem inputted from the operation unit to the Ising model, inputs the Ising model produced by conversion and initial operating conditions into the computation unit, and has the computation unit search for the ground state using overall operating conditions produced by changing the initial operating conditions based on a result of the computation unit searching for the ground state using the initial operating conditions.

Optimization apparatus and control method for optimization apparatus using ising models

An optimization method includes holding combining destination information indicating a combining destination neuron to be combined with a target neuron which is one of a plurality of neurons corresponding to a plurality of spins of an Ising model obtained by converting an optimization problem, the target neuron being different in a plurality of neuron circuits; holding a weighting coefficient indicating a strength of combining between the target neuron and the combining destination neuron, and outputting the weighting coefficient corresponding to the combining destination information; permitting an update of a value of the target neuron by using the weighting coefficient output and the value of the update target neuron, and outputting a determination result indicating whether or not the value of the target neuron is permitted to be updated; and determining the update target neuron based on the plurality of determination results respectively output and outputting the update target information.

Optimization apparatus and optimization method

An optimization device includes: processing circuits each configured to: hold a first value of a neuron of an Ising model; and perform a process to determine whether to permit updating of the first value based on information of the Ising model and information about a target neuron; a control circuit configured to: set, while causing a portion of the processing circuits to perform the process for a partial neuron group, information to be used for the process for a first neuron other than the partial neuron group in a first processing circuit; cause a second processing circuit among the portion of the processing circuits to inactivate the process; and cause the first processing circuit to start the process for the first neuron; and an update neuron selection circuit configured to: select the target neuron from one or more update permissible neurons; and update the value of the target neuron.

Optimization device and control method of optimization device

An individual ising device connected to common buses includes neuron circuits, a memory, and a router. The memory holds connection destination information per neuron circuit. An individual item of connection destination information includes first address information identifying one of a plurality of connection destination neuron circuits of a neuron circuit and second address information identifying a first ising device including at least one of the connection destination neuron circuits, the first and second address information being correlated. The router supplies, when an output signal of a connection destination neuron circuit changes and when the router receives the first address information identifying this connection destination neuron circuit via a bus, an update signal based on the changed output signal to one of the neuron circuits in accordance with the received first address information, the previously specified second address information identifying the first ising device, and the connection destination information.

Information processing apparatus, ising device, and control method for information processing apparatus

Boltzmann machine includes a plurality of circuit units each having an adder that adds weighted input signals and a comparison unit that compares an output signal of the adder with a threshold signal to output a binary output signal; and digital arithmetic units each generating the weighted input signals by weighting the binary output signal of the circuit units with a weight. The comparison unit has a first comparator that compares a thermal noise with a reference voltage to output a binary digital random signal, a DA converter that converts the digital random signal to an analog random signal and varies a magnitude of the analog random signal, and a second comparator that compares the output signal of the adder with the analog random signal to generate the binary output signal with a predetermined probability function.

Boltzmann machine, method for controlling boltzmann machine, and information processing device having boltzmann machine

Arithmetic circuits calculate d&#x2212;1 energy values (hto h) indicating energies generated by 2-body to d-body coupling on the basis of a plurality of weight values indicating strength of 2-body to d-body coupling of 2 to d neurons including a first neuron whose output value is allowed to be updated and n-bit output values of n neurons. An adder circuit calculates a sum of these values, and a comparator circuit compares a value based on a sum of the sum and a noise value with a threshold, to determine the output value of the first neuron. An update circuit outputs n-bit updated output values in which one bit has been updated on the basis of a selection signal and the output value of the first neuron. The holding circuit holds the updated output values and outputs the updated output values as the n-bit output values used by the arithmetic circuits.

Information processing apparatus, ising device, and information processing apparatus control method

A jitter measurement circuit includes an addition circuit to add a digital rectangular signal to an adjustment signal generated by a circuit that generates a first error signal based on a phase difference between a first clock signal or a data signal on which the first clock signal is superimposed and a second clock signal and generates the adjustment signal by filtering the first error signal, and a calculation circuit to calculate a first correlation value for representing an autocorrelation of the first error signal when the rectangular signal is not added to the adjustment signal, and a second correlation value for representing the autocorrelation when the rectangular signal is added to the adjustment signal, based on the first error signal and a second error signal obtained by delaying the first error signal by a variable delay amount, and output the first correlation value and the second correlation value.

Jitter measurement circuit and jitter measurement system

A Boltzmann machine circuit includes: a plurality of circuits each circuit configured to add one or more first values based on one or more outputs of one or more circuits which are included in the plurality of circuits and are other than the circuit and convert an addition result into an analog signal, compare the analog signal with a second value, and output a comparison result; a plurality of arithmetic circuits configured to multiply the respective comparison results by respective weight values and generate the first values; and a control circuit configured to amplify an amplitude of the analog signal generated by each of the plurality of circuits.

Boltzmann machine circuit

An A/D converter includes an A/D conversion unit, a histogram generation-storage unit, and a control unit. The A/D conversion unit is configured to receive an input voltage, perform an analog-to-digital conversion, and output digital data, and the histogram generation-storage unit is configured to receive the digital data, generate a histogram for a waveform of the input voltage, and store the generated histogram therein. The control unit is configured to control an analog-to-digital conversion characteristics of the A/D conversion unit, based on the histogram stored in the histogram generation-storage unit.

A/D converter and A/D converter calibrating method

An interpolation circuit includes: a plurality of holding circuits configured to each hold a corresponding input data input chronologically; and a generating circuit configured to generate interpolation data by giving weights, based on an interpolation code, to input data that are chronologically adjacent to each other and are held by the plurality of holding circuits and combining the weighted data together.

Interpolation circuit and receiving circuit

There is provided a receiving device includes: a plurality of interpolation unit circuits, each interpolation unit circuit configured to perform interpolation processing of a sampling value obtained by asynchronously sampling input data, based on an interpolation ratio, so that sampling data synchronous with the input data and continuous in time is generated, wherein one of the interpolation unit circuits is provided in parallel with another of the interpolation unit circuits for a channel previous to a channel in which switching of the interpolation ratio is performed.

Receiving device and data interpolation processing method

An electronic circuit includes: a weighting circuit configured to generate a first current by weighting and combining a first input signal and a second input signal in accordance with a modifiable coefficient and to generate a second current by weighting and combining a first inverted signal and a second inverted signal in accordance with the coefficient, the first inverted signal being an inverted signal of the first input signal, the second inverted signal being an inverted signal of the second input signal; and a decision circuit configured to decide on an output signal by comparing the first current with the second current.

Electronic circuit

An analog-to-digital converter includes a digital-to-analog (DA) converting part having a predetermined number of gradation converting stages and configured to cause each of the predetermined number of gradation converting stages to convert a digital signal to an analog signal and output the converted analog signal, a main-comparator configured to output a binary signal on the basis of a first comparison result between the analog signal output from the DA converting part and a predetermined reference level, and a second sub-comparator having an offset less than a quantization unit with respect to the main-comparator and being configured to output a binary signal on the basis of a second comparison result between the analog signal output from the DA converting part and the predetermined reference level.

Analog-to-digital converter and electronic apparatus

A successive approximation A/D converter, has a main DAC having a capacitive element group coupled to a top node and a switch group; a comparator comparing voltage of the top node with comparison reference voltage; a correction DAC generating correction voltage in accordance with a capacitance error of a capacitive element pair to be balanced in the main DAC, and supplying the correction voltage to the top node; and a control circuit generating internal digital input for controlling the switch group and a correction code for controlling the correction voltage, and outputting a successive approximation result by the comparator when the A/D conversion is performed. The control circuit measures a capacitance error of the capacitive element pair to be balanced, and determines an offset-removed capacitance error where an offset generated in the measurement is removed from the capacitance error.

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Setagaya, Japan

Sanroku Tsukamoto