Rambus Inc.

Qualcomm Incorporated

Sanku Mukherjee

Ian P Shaeffer

Arun Vaidyanath

Madan Krishnappa

Santanu Pattanayak

Vishal Ghorpade

Uttkarsh Wardhan

Pankhuri Agarwal

Lakshmi Neeharika Gamini

Sanath Sreekanta

Arvind Garg

Sanath Sreekanta Bangalore

Various embodiments include methods that may be performed by a DRAM controller of a computing device for reducing power consumption in restore operations after a memory access. The method may control the memory charge restoration of a memory, by determining a time position within a refresh window of a read operation of at least one memory cell of the memory, charging the at least one memory cell to a first voltage that is based on the time position of the read operation within the refresh window; and re-charging the at least one memory cell to a full voltage upon termination of the refresh window, such that the first voltage is less than the full voltage in a first portion of the refresh window.

Refresh window aware truncation of restore voltages for random access memory

A method performed by a machine learning system includes generating a set of reward values based on a set of parameter values selected by a machine learning system, each reward value of the set of reward values corresponding to a parameter value of the set of parameter values programmed at a device. The method also includes determining a reward function for maximizing a reward corresponding to a set of parameters of the device based on the set of reward values. The method further includes tuning a parameter of the set of parameters based on the reward function.

Reinforcement learning based scheme for tuning memory interfaces

An expandable memory system that enables a fixed signaling bandwidth to be configurably re-allocated among dedicated memory channels. Memory channels having progressively reduced widths are dedicated to respective memory sockets, thus enabling point-to-point signaling with respect to each memory socket without signal-compromising traversal of unloaded sockets or costly replication of a full-width memory channel for each socket.

Buffer IC with asymmetric memory module interfaces

The reliability of a data communication link may be analyzed and otherwise maintained by collecting a two-dimensional array representing a functional data eye, and using a convolutional neural network to determine a score of the functional data eye. The determined score may be compared with a threshold, and an action may be initiated based on the result of the comparison.

Data link stability detection using computer vision-based data eye analysis

Asymmetric-channel memory system

An integrated-circuit buffer component includes a control-side data interface configurably coupled to first and second memory-side data interfaces via internal conductors, the first data interface having twice as many input/output (I/O) transceivers as the second data interface. In a first memory system configuration in which only the first data interface is coupled to a memory module, steering circuitry couples all the internal data conductors exclusively to the I/O transceivers of the first data interface. In a second memory system configuration in which the first and second data interfaces are coupled to respective memory modules, the steering circuitry couples a first half of the internal data conductors exclusively to the I/O transceivers of the second data interface while a second half of the internal data conductors remains exclusively coupled to half the I/O transceivers of the first data interface.

Buffer component for asymmetric-channel memory system

In calibrating the phase skew between an SDRAM data strobe ('DQS') signal and data ('DQ') signal in a device, the data signal driver circuit impedance is adjusted to impair impedance matching on the DQ signal channel while system-level memory tests are performed. The phase skew is stepped through a range during the memory tests, and an error count is determined for each test. The memory tests may emulate mission-mode operation of the device. Following the memory tests, an optimal phase skew corresponding to a lowest error count is determined. The DQS signal may be delayed with respect to the DQ signals by a value corresponding to the optimal phase skew in subsequent mission-mode operation of the device.

Double data rate synchronous dynamic random access memory ('DDR SDRAM') data strobe signal calibration

A memory-control integrated circuit includes internal data conductors, steering circuitry and distinct first and second data interfaces, the first data interface having twice as many input/output (I/O) transceivers as the second data interface. In a first memory system configuration in which only the first data interface is coupled to a memory module, the steering circuitry couples all the internal data conductors exclusively to the I/O transceivers of the first data interface. In a second memory system configuration in which the first and second data interfaces are coupled to respective memory modules, the steering circuitry couples a first half of the internal data conductors exclusively to the I/O transceivers of the second data interface while a second half of the internal data conductors remains exclusively coupled to half the I/O transceivers of the first data interface.

Growing community of inventors

Bengaluru, India

Sanku Mukherjee