Xilinx, Inc.

Sanket Pandit

Elliott Delaye

Aaron Ng

Ehsan Ghasemi

Xiao Teng

Rajeev Patwari

Jorn Tuyls

Satyaprakash Pareek

Tejus Siddagangaiah

Bryan Lozano

Pramod Peethambaran

Controlling a data processing (DP) array includes creating a replica of a register address space of the DP array based on the design and the DP array. A sequence of instructions, including write instructions and read instructions, is received. The write instructions correspond to buffer descriptors specifying runtime data movements for a design for a DP array. The write instructions are converted into transaction instructions and the read instructions are converted into wait instructions based on the replica of the register address space. The transaction instructions and the wait instructions are included in an instruction buffer. The instruction buffer is provided to a microcontroller configured to execute the transaction instructions and the wait instructions to implement the runtime data movements for the design as implemented in the DP array. In another aspect, the instruction buffer is stored in a file for subsequent execution by the microcontroller.

Instruction set architecture for data processing array control

An integrated circuit includes a plurality of kernels and a virtual machine coupled to the plurality of kernels. The virtual machine is configured to interpret instructions directed to different ones of the plurality of kernels. The virtual machine is configured to control operation of the different ones of the plurality of kernels responsive to the instructions.

Reconfigurable neural engine with extensible instruction set architecture

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San Jose, CA, United States of America

Sanket Pandit