Synopsys, Inc.

Hewlett-packard Development Company, L.p.

Sanket Naik

Biman Chattopadhyay

Ravi Mehta

Gopal Krishna Ullal Nayak

Vijay A Nebhrajani

John Theodore Stonick

Fernando Juan

Edward Dale Davis

Jayesh Gangaprasad Wadekar

Michael W Lynch

Ayal S Shoval

Akarsh Joshi

Sujoy Chakravarty

Adam Ross Burns

Megha Jaiswal

Rishi Sharma

Ankit Somani

Ameer Muhammad Youssef

A re-timer device includes transceiver circuitry. The transceiver circuitry includes clock generation circuitry and first receiver circuitry. The clock generation circuitry generates a first clock signal. The first receiver circuitry receives the first clock signal and a first input signal. The first receiver circuitry generates a first frequency offset value based on the first input signal and the first clock signal. The first input signal has a first frequency and the first clock signal has a second frequency different than the first frequency. The first receiver circuitry outputs the first frequency offset value.

Transceiver devices with transmitter and receiver frequency control

A printing system may be provided. The printing system may include an agent distributor to selectively deliver at least one printing agent onto a substrate on a first type of supply module and a layer of build material on a second type of supply module. The printing system may include a controller to control the agent distributor to selectively deliver the at least one printing agent in patterns derived from data representing a slice of a three-dimensional object to be generated and representing an image to be generated on the substrate.

Generating three-dimensional objects and generating images on substrates

A multi-modulus frequency divider circuit includes first and second frequency division stages. The first frequency division stage receives a first input clock signal having a first oscillating frequency, a first modulus input signal, and a first division bit. The first frequency division stage divides the first oscillating frequency by a first division ratio, and generates a second input clock signal having a second oscillating frequency. The second frequency division stage receives the second input clock signal, a second modulus input signal, and a second division bit. The second frequency division stage generates an output clock signal having an output oscillating frequency by dividing the second oscillating frequency by a second division ratio.

Multi-modulus frequency divider circuit

A clock and data recovery (CDR) circuit includes first through ninth samplers, a clock recovery circuit, a level finding circuit, an offset voltage generator, and a data recovery circuit. Each of the first through ninth samplers samples a data signal based on one of first through ninth reference offset voltage levels to generate first through ninth intermediate signals, respectively. The clock recovery circuit generates the first through fourth clock signals based on the first, second, fifth, and eighth intermediate signals. The level finding circuit generates a band level signal by varying the third intermediate signal. The offset voltage generator generates one of: the fourth and seventh reference offset voltage levels, the fifth and eighth reference offset voltage levels, and the sixth and ninth reference offset voltage levels based on the band level signal. The data recovery circuit detects an output data signal based on the fourth through ninth intermediate signals.

Multi-level clock and data recovery circuit

Programmable shift register with programmable load location (pSRL) for data storage and method thereof is disclosed. A loadable programmable Shift Register (pSR) according to present disclosure receives a programmable input LL that defines where data D is to be loaded from the Load Register when L (Load Control Signal)=1. The loadable Shift Register with programmable load location (pSRL) is configured to obtain L (Load Control Signal), S (Shift Control Signal), LL (Load Location Control Signal), and p (programmable shift value), and wherein the pSRL is adapted to perform loading and shifting of data D based at least on the L, S, LL, and p values.

Programmable shift register with programmable load location

The present disclosure pertains to a programmable data width converter device, system and method thereof. Programmable data width converter (pDWC) of the present disclosure can include a control Finite State Machine (FSM) that is configured to receive input values of m and n, and control any or a combination of L (Load Control Signal), S (Shift Control Signal), LL (Load Location Control Signal), and p (programmable shift value) based on the received values of m and n; and a loadable programmable shift register with programmable load location (pSRL) operatively coupled with the control FSM, wherein the pSRL is configured to perform loading and shifting functions based on the L, S, LL, and p values loaded by the control FSM. The pDWC can be configured to programmably convert width of m k-bit word input to n k-bit word output, and wherein 1&#x2264;m&#x2264;M and 1&#x2264;n&#x2264;N.

Programmable data width converter device, system and method thereof

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Bengaluru, India

Sanket Naik