Raytheon Company

Texas Instruments Corporation

Sankerlingam Rajendran

James A Carr

Karl L Worthen

Cary C Kyhl

Douglas R Gentry

Brian K Atwood

Thang D Nguyen

Walter B Aschenbeck, Jr

John Michael Bedinger

Mark B Hanna

Billy D Ables

Patrick J Kocurek

Thomas A Hanft

Susan M Eshelman

Monte R Sanchez

Van T Vo

Rajiv S Shah

A conductive network fabrication process is provided and includes filling a hole formed in a substrate with dielectric material, laminating films of the dielectric material on either side of the substrate, opening a through-hole through the dielectric material at the hole, depositing a conformal coating of dielectric material onto an interior surface of the through-hole and executing seed layer metallization onto the conformal coating in the through-hole to form a seed layer extending continuously along an entire length of the through-hole.

Double-sided, high-density network fabrication

A circulator is provided, comprising, first second and third conductors forming three equally spaced junctions and a permanent magnet configured to apply a shaped bias magnetic field to a ferrite resonator in operable communication with the first, second, and third conductors. The permanent magnet comprises a substantially planar monolithic structure having defined thereon at least first and second substantially concentric regions having first and second respective magnetic field strength levels, wherein the second magnetic field strength level is lower than the first magnetic field strength level. The first and second magnetic field strength levels are configured to cooperate to shape an external bias magnetic field of the permanent magnet to counteract at least a portion of a demagnetizing effect resulting from of an overall shape of the ferrite resonator, to achieve a substantially uniform internal magnetic bias within at least a portion of the ferrite resonator.

Shaped magnetic bias circulator

A method for making a composite substrate circulator comprising disposing a plurality of sleeves about a plurality of rods, disposing the plurality of rods and the plurality of sleeves in a plurality of openings in a block to form an assembly, and dividing the assembly to form a plurality of plates. Each plate includes a portion of the plurality of sleeves and the plurality of rods. The magnetic saturation (4PiMs) values of the rods and sleeves are chosen to decrease radially (rod has the highest 4PiMs).

Method for making a composite substrate circulator component

A method of lamination of dielectric circuit materials is provided. The method includes preparing first and second circuit layers of dielectric materials, stacking the first and second circuit layers with circuit trace elements interposed between the first and second circuit layers and ultrasonically welding the second circuit layer onto the first circuit layer around the circuit trace elements.

Method of lamination of dielectric circuit materials using ultrasonic means

A stacked stripline circulator includes a first ferrite disc, a second ferrite disc, a first substrate having a metalized edge with the first ferrite disc disposed in the first substrate, a second substrate having a metalized edge with the second ferrite disc disposed in the second substrate, a first metalized pattern defining ports of a circulator disposed on the first substrate, the first metalized pattern comprising copper, a second metalized pattern defining ports of a circulator disposed on the second substrate, the second metalized pattern comprising copper, and a bonding ring bonding the metalized edge of the first substrate with the metalized edge of the second substrate.

Stacked low loss stripline circulator

Integrating a semiconductor component with a substrate through a low loss interconnection formed through adaptive patterning includes forming a cavity in the substrate, placing the semiconductor component therein, filling a gap between the semiconductor component and substrate with a fill of same or similar dielectric constant as that of the substrate and adaptively patterning a low loss interconnection on the fill and extending between the contacts of the semiconductor component and the electrical traces on the substrate. The contacts and leads are located and adjoined using an adaptive patterning technique that places and forms a low loss radio frequency transmission line that compensates for any misalignment between the semiconductor component contacts and the substrate leads.

Heterogeneous chip integration with low loss interconnection through adaptive patterning

According to one embodiment, a pattern forming system includes a patterning tool, a multi-axis robot, and a simulation tool that are coupled to a pattern forming tool that is executed on a suitable computing system. The pattern forming tool receives a contour measurement from the patterning tool and transmits the measured contour to the simulation tool to model the electrical characteristics of a conductive pattern or a dielectric pattern on the measured contour. Upon receipt of the modeled characteristics, the pattern forming system may adjust one or more dimensions of the pattern according to the model, and subsequently create, using the patterning tool, the corrected pattern on the surface.

System for forming patterns on a multi-curved surface

A method of forming an electrically conductive via with bumps on both sides of a substrate wherein there is provided a substrate having a pair of opposing surfaces and a via extending between the opposing surfaces. A layer of a material capable of forming a seed for receiving thereon a plating material is provided on one of the surfaces extending to the via. The structure is then placed into an electroplating bath, preferably gold-containing, to electroplate the walls of the via. The electroplated material is then heated to a temperature above its flow or melting temperature in a reducing atmosphere for a time sufficient to cause the electroplated material to fill the via and any voids within the via. The step of heating the electroplated material is preferably to a temperature at least 10 degrees C. above its flow or melting temperature of the electroplated material. The reducing atmosphere is from about 5 percent to 100 percent hydrogen and the remainder preferably nitrogen. The step of electroplating can include electroplating of sufficient electroplated material in the via to provide a bump on at least one of the surfaces heating.

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Plano, TX, United States of America

Sankerlingam Rajendran