Intel Corporation

Sanjoy K Mondal

Gilbert A Neiger

Jason W Brandt

Richard A Uhlig

Robert T George

Lawrence O Smith

Rajesh Bhikhubhai Patel

Vedvyas Shanbhogue

Andrew V Anderson

Steven M Bennett

Wei Ey Li

Erik C Cota-Robles

Stalinselvaraj Jeyasingh

Belliappa Manavattira Kuttanna

Ashish V Choubal

Robert L Farrell

Bruce L Fleming

Arvind Raman

Alain Kägi

Jeff Huxel

Venkateswara Rao Madduri

Dion Rodgers

Jonathan D Combs

Lance E Hacking

Sankaran M Menon

Rajesh S Parthasarathy

Larry Edward Thatcher

Peter J Ruscito

Eric L Hendrickson

Jason W Brandit

William Hodges

Stalinselvaraj Jayasingh

In one embodiment, a processor includes at least one core and an interface circuit to interface the at least one core to additional circuitry of the processor. In response to an in-field self test instruction, at least one core may save state to a low power memory, enter into a diagnostic sleep state and execute an in-field self test in the diagnostic sleep state in which the at least one core appears to be inactive. Other embodiments are described and claimed.

System, apparatus and method for in-field self testing in a diagnostic sleep state

In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.

Maintaining processor resources during architectural events

A method and apparatus is described herein for accessing a physical memory location referenced by a physical address with a processor. The processor fetches/receives instructions with references to virtual memory addresses and/or references to physical addresses. Translation logic translates the virtual memory addresses to physical addresses and provides the physical addresses to a common interface. Physical addressing logic decodes references to physical addresses and provides the physical addresses to a common interface based on a memory type stored by the physical addressing logic.

Accessing physical memory from a CPU or processing element in a high performance manner

Method and apparatus for accessing physical memory from a CPU or processing element in a high performance manner

Maintaining processor resources during architectural evens

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San Marcos, TX, United States of America

Sanjoy K Mondal