Xilinx, Inc.

Sanjiv Stokes

Mohsen Hossein Mardi

Henley Liu

Xin X Wu

Hassan K Bazargan

Chih-Chung Wu

Jae Cho

Shih-Liang Liang

Steven P Young

Paul Y Wu

Myongseob Kim

Cheang-Whang Chang

Christopher Paul Wyland

Ramakrishna K Tanikella

Khaldoon S Abugharbieh

Yong Wang

Gregory Meredith

An integrated circuit includes a die having a conductive layer. The conductive layer includes a data wire, a first power supply wire of a first voltage potential, and a second power supply wire of a second voltage potential different from the first voltage potential. A segment of the data wire is located between, and substantially parallel to, a segment of the first power supply wire and a segment of the second power supply wire. Further, the first power supply wire is coupled to a first probe structure; and, the second power supply wire is coupled to a second probe structure.

Shielded wire arrangement for die testing

An embodiment of an apparatus to reduce supply voltage noise with capacitors of an interposer of a stacked die is disclosed. In this embodiment, an interposer is coupled to a first integrated circuit die using a first plurality of interconnects. A substrate is coupled to the interposer using a second plurality of interconnects. The substrate includes a supply voltage plane and a ground plane, each of which is coupled to the first integrated circuit die using the second plurality of interconnects, the interposer, and the first plurality of interconnects. The interposer includes capacitors coupled in parallel using the supply voltage plane, the ground plane, and the second plurality of interconnects, where capacitance from capacitors of the interposer is provided to the first integrated circuit die using the supply voltage plane and the ground plane of the substrate.

Capacitors within an interposer coupled to supply and ground planes of a substrate

A semiconductor component having test pads and a method and apparatus for testing the same is described. In an example, an un-bumped substrate is obtained having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. In another example, a substrate is fabricated having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. An insulating layer is formed over the plurality of test pads.

Semiconductor component having test pads and method and apparatus for testing same

An interconnect structure in which 'diagonal' and 'straight' interconnect lines are interleaved to minimize coupling between adjacent interconnect lines. An interconnect structure for an integrated circuit comprises rows and columns of tiles. Interconnect lines extend at least in part along a first column of the tiles, the interconnect lines including straight and diagonal interconnect lines. A &#x201c;straight&#x201d; interconnect line interconnects at least two tiles in the first column, and a &#x201c;diagonal&#x201d; interconnect line interconnects a tile in the first column with at least one tile in a different column and row. The interconnect lines are laid out in parallel fashion such that no straight interconnect line is physically adjacent to more than one other straight interconnect line, and no diagonal interconnect line is physically adjacent to more than one other diagonal interconnect line. Optionally, no two physically adjacent interconnect lines drive in the same direction within the first column.

Integrated circuit interconnect structure having reduced coupling between interconnect lines

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Los Altos, CA, United States of America

Sanjiv Stokes