Dell Products Inc.

Sanjiv Sinha

Sandor Tibor Farkas

Corey Dean Hartman

John Ross Palmer

Syed S Ahmed

James Lewis Petivan

Bhyrav M Mutnury

Mukund Purshottam Khatri

Timothy Michael Lambert

Stuart Allen Berke

John Erven Jenne

Lei Wang

Jeffrey Leighton Kennedy

Robert G Bassman

Michael Joseph Stumpf

Salvador D Jimenez, Iii

William Andrew Smith

Mark A Smith

Noman Mithani

Methods and systems for managing power distribution and/or mechanical load in data processing systems is provided. The power distribution may be managed using multifunction power buses that may relieve a motherboard of a data processing system from distributing power. The mechanical load may be managed using an adapter plate that may relieve the motherboard of the data processing system from providing for attachment of devices based on the location of the mechanical mounting hardware on the devices. By doing so, motherboards may be standardized and customized for use with various devices.

System and method for mechanical support in configurable systems

Methods and systems for providing computer implemented services using configurable hardware components are disclosed. To update operation of a configurable hardware component, a large amount of data may be provided to a single input/output pin of the configurable hardware component. The large amount of data may be encoded in a complex waveform corresponding with at least eleven bits of digital data. The complex waveform may be interpreted by the configurable hardware component to obtain the large amount of data. Using the large amount of data, the configurable hardware component may update its operation to be in condition for providing the computer implemented services.

System and method for providing operation information to configurable devices

An information handling system may include a host processor module comprising a host processor field programmable gate array, a management controller communicatively coupled to the host processor field programmable gate array and configured to provide out-of-band management facilities for management of the information handling system, and an interposer configured to interface between the host processor field programmable gate array and one or more peripheral devices in order to perform power management and control of the one or more peripheral device. The interposer may include a general purpose input/output extender configured to enable and control power delivery to the one or more peripheral devices and a microcontroller unit communicatively coupled to the host processor field programmable gate array and configured to perform monitoring and discovery of the one or more peripheral devices.

Systems and methods for granular and scalable subsystem power controls, fault handling, and field-replaceable unit isolation in a modular architecture

System and method for power distribution in configurable systems

A connection assembly, including: a first connector having a first end and a second end, and a first surface extending between the first end and the second end, the first connector including press fit pins extending away from the first surface, each of the press fit pins including: a rod portion; a connecting portion having a first shape; a second connector having a first end and a second end, including: a dielectric carrier having a first surface extending between the first end and the second end of the second connector, receptacles positioned within the first surface of the dielectric carrier, each of the receptacles including: a cylindrical region, a tapered region having a second shape that corresponds to the first shape of the connection portion, wherein, when the first connector is coupled to the second connector, the press fit pins are positioned within respective receptacles of the receptacles.

Connection assembly for an information handling system

A floating device location identification system includes a chassis defining floating device housings and including respective chassis location identification features adjacent each floating device housing that identify the relative location of that floating device housing. A floating device may be positioned in a first floating device housing and adjacent a first chassis location identification feature. The first floating device includes floating device cabling connector(s) that are connected via a cabling subsystem to a device location identification subsystem, and chassis engagement elements that are coupled to the floating device cabling connector(s) and that engage the first chassis location identification feature. The floating device transmits floating device location identifying information to the device location identification subsystem that is based on the engagement of the chassis engagement elements and the first chassis location identification feature, and that identifies a relative location of the first floating device housing in the chassis.

Floating device location identification system

A method and an information handling system (IHS) provides a virtual alternating current (vAC) reset of the IHS. A vAC reset module (vACRM), in response to receiving a request for the vAC reset, sets a bit within an auxiliary (AUX) based register to invoke the vAC reset when a system restart command is issued. The vACRM changes/configures a vAC recovery policy to enable main rail power to be turned on and a system start-up procedure to be initiated when a restored vAC is detected. The vACRM uses a system restart command to shutdown the main rail power and to remove power from system components powered by the main rail. The vACRM switches off AUX power to AUX powered components, based on the previously set bit, and reapplies the AUX power, following a preset interval. The vACRM turns on main rail power and initiates a system start-up procedure, according to the vAC recovery policy.

Virtual AC cycling within an information handling system

Memory short detection systems and methods include a power supply system with first power rail. A memory system includes a memory device connector that is configured to couple to a memory device and includes a first pin that is coupled to the first power rail and a second pin located adjacent the first pin. A short detection circuit is coupled to the first pin. The short detection circuit is configured to provide a first voltage from the first power rail, compare the first voltage to a first short detection voltage, and determine whether a short exists across the first pin and the second pin based on the comparing of the first voltage to the first short detection voltage. If a short is determined to exist across the first pin and the second pin, power is prevented from being provided to the memory device connector.

Memory short protection system

In accordance with embodiments of the present disclosure, a battery back-up unit for supplying electrical energy to an information handling resource via a power bus in response to a power event affecting an ability of a power supply unit to deliver electrical energy to the information handling resource via the power bus may be configured to, in response to the power event and prior to the power supply unit ceasing to deliver electrical energy to the power bus monitor a current share bus having a current share signal driven at least in part by the power supply unit, the current share signal indicative of a first current driven by the power supply unit to the power bus, drive a second current to the power bus in accordance with the current share signal, and refrain from driving the current share bus.

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Austin, TX, United States of America

Sanjiv Sinha