Atrenta, Inc.

Synopsys, Inc.

Sanjiv Mathur

Ravi Varadarajan

Jitendra Kumar Gupta

Anup Nagrath

Kshitiz Krishna

Chun-Cheng Chi

Shih-Pin Hung

Sivakumar Arulanantham

Priyank Mittal

Kaushal Kishore Pathak

Ritesh Mittal

Ashima Dabare

Srinivasan Krishnamurthy

Prakasha Karkada Holla

Anusha Reddy Sindhwala

Ashima Sahil Dabare

Embodiments provide for building a global clock tree. In embodiments, an example method includes inserting clock drivers at symmetric locations in one or more hierarchy levels of a plurality of hierarchy levels of an integrated circuit (IC) design. The example method further includes generating one or more routes by routing one or more nets within or across the one or more hierarchy levels of the plurality of hierarchy levels. The example method further includes matching symmetric routes of the one or more routes at each of the one or more hierarchy levels irrespective of a number of physical hierarchies each associated net spans. The example method further includes placing one or more ports at one or more signal entry points where routes of the one or more routes cross physical hierarchy blocks.

Automated balanced global clock tree synthesis in multi level physical hierarchy

A method for timing optimization of an integrated circuit design using a timing optimization system comprising loading an original delay value and an original gate configuration net-list for an original gate from a results database. A near optimum gate configuration is identified using near optimum gate configuration information stored in a delay characterization database for the original gate. A near optimum delay value and a near optimum gate configuration net-list of a near optimum gate configuration are loaded. A timing optimized gate configuration is provided from running an incremental static timing analysis of the near optimum gate configuration.

Characterization based buffering and sizing for system performance optimization

System-on-chip (SoC) designs include large amounts of interconnected intellectual property blocks and standard-cell logic using complex bus fabrics. Today SoC design-closure that validates design targets of area, timing, congestion and power constraints is accomplished post routing as over 80% of validation problems are due to global-interconnect. A method is disclosed that allows the designers to achieve global design-closure and physical topology constraints, early in the design cycle, at much higher levels of abstraction. In particular, logic hierarchy of the design is converted into a physical hierarchy of functional-related clusters of locally-connected logic. The clusters and inter-cluster global connections can be refined to meet design constraints in order to generate a top-level floor-plan in the form of library and constraint files. Using the results of this top-down global design-closure method the designers can use the generated floor-plan to guide downstream tools to achieve predictable and correlatable design implementation.

Method of global design closure at top level and driving of downstream implementation flow

This invention provides a method for detecting physical implementation hot-spots in a pre-placement integrated circuit design. The method first identifies physical issues at an object level. Physical issues include timing, routing congestion, clocking, scan, power, and thermal. The method then analyzes these physical issues over a collection of connected logic cell and large cell instances and determines a physical implementation hot-spot severity based on the number and severity of physical issues as well as the number of objects in the related collection.

Efficient method to analyze RTL structures that cause physical implementation issues based on rule checking and overlap analysis

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Noida, India

Sanjiv Mathur