Oracle America, Inc.

Oracle International Corporation

Sun Microsystems, Inc.

Sanjiv Kapil

Garret Frederick Swart

Ricky C Hetherington

Kathirgamar Aingaran

Robert Paul Masleid

Sumti Jairath

William Havinden Bridge, Jr

John Johnson

David J Greenhill

Zoran Radovic

Blake Alan Jones

Darryl J Gove

Aaron S Wynn

Aings Aingaran

John G Johnson

William H Bridge

The disclosed embodiments relate to a computing system that facilitates performing prefetching for scatter/gather operations. During operation, the system receives a scatter/gather prefetch instruction at a processor core, wherein the scatter/gather prefetch instruction specifies a virtual base address, and a plurality of offsets. Next, the system performs a lookup in a translation-lookaside buffer (TLB) using the virtual base address to obtain a physical base address that identifies a physical page for the base address. The system then sends the physical base address and the plurality of offsets to a cache. This enables the cache to perform prefetching operations for the scatter/gather instruction by adding the physical base address to the plurality of offsets to produce a plurality of physical addresses, and then prefetching cache lines for the plurality of physical addresses into the cache.

Facilitating efficient prefetching for scatter/gather operations

Techniques for processing a query are provided. One or more operations that are required to process a query are performed by a coprocessor that is separate from a general purpose microprocessor that executes query processing software. The query processing software receives a query, determines one or more operations that are required to be executed to fully process the query, and issues one or more commands to one or more coprocessors that are programmed to perform one of the operations, such as a table scan operation and/or a lookup operation. The query processing software obtains results from the coprocessor(s) and performs one or more additional operations thereon to generate a final result of the query.

Hardware for performing a database operation

A system and method for transferring data and messages between nodes in a cluster is disclosed. Each node in the cluster is a separate physical domain but is connected to other nodes in the cluster through point-to-point high speed links. Each side of a link is coupled to a coprocessor which facilitates the movement of data between and among the nodes. Because each physical domain is separate from any other domain, the coprocessor in a physical domain uses a certificate, called and RKey, to obtain permission to transfer data to another physical domain. When an RKey is received from another physical domain, the coprocessor in the receiving domain validates the key and obtains the physical addresses associated with the key so that it can provide or accept the remote data. Data transfers between pairs of remote nodes in the cluster are permitted as well.

Memory bus protocol to enable clustering between nodes of distinct physical domain address spaces

A system and method implementing revocable secure remote keys is disclosed. A plurality of indexed base secrets is stored in a register of a coprocessor of a local node coupled with a local memory. When it is determined that a selected base secret expired, the base secret stored in the register based on the base secret index is changed, thereby invalidating remote keys generated based on the expired base secret. A remote key with validation data and a base secret index is received from a node requesting access to the local memory. A validation base secret is obtained from the register based on the base secret index. The coprocessor performs hardware validation on the validation data based on the validation base secret. Hardware validation fails if the base secret associated with the base secret index has been changed in the register of the selected coprocessor.

Remote-key based memory buffer access control mechanism

A computer system with flash memory in the main memory hierarchy is disclosed. In an embodiment, the computer system includes at least one processor, a memory management unit coupled to the at least one processor, and a random access memory (RAM) coupled to the memory management unit. The computer system may also include a flash memory coupled to the memory management unit, wherein the computer system is configured to store at least a subset of a plurality of pages in the flash memory during operation. Responsive to a page fault, the memory management unit may determine, without invoking an I/O driver, if a requested page associated with the page fault is stored in the flash memory and further configured to, if the page is stored in the flash memory, transfer the page into RAM.

Extended main memory hierarchy having flash memory for page fault handling

Hardware for table scan acceleration

A memory system that interleaves storage of data across and within a plurality memory modules is described. The memory system includes a hybrid interleaving mechanism which maps physical addresses to locations within memory modules and ranks so that physical addresses for a given page all map to the same memory module, and physical addresses for the given page are interleaved across the plurality of ranks which comprise the same memory module.

Hybrid interleaving in memory modules by interleaving physical addresses for a page across ranks in a memory module

The described embodiments include a system that modulates the width of a high-speed link. The system includes a transmitter circuit coupled to a high-speed link that includes N serial lanes. During operation, while using a first number of lanes to transmit frames on the high-speed link, the transmitter circuit determines a second number of lanes to be used to transmit frames on the high-speed link based on a bandwidth demand on the high-speed link. The transmitter circuit then sends an indicator of the second number of lanes to a receiver on the high-speed link. Upon receiving an error-free acknowledgment of the indicator from the receiver, starting from a predetermined frame, the transmitter circuit transmits subsequent frames on the high-speed link using the second number of lanes.

Method and apparatus for modulating the width of a high-speed link

System and method for using flash memory in a memory hierarchy. A computer system includes a processor coupled to a memory hierarchy via a memory controller. The memory hierarchy includes a cache memory, a first memory region of random access memory coupled to the memory controller via a first buffer, and an auxiliary memory region of flash memory coupled to the memory controller via a flash controller. The first buffer and the flash controller are coupled to the memory controller via a single interface. The memory controller receives a request to access a particular page in the first memory region. The processor detects a page fault corresponding to the request and in response, invalidates cache lines in the cache memory that correspond to the particular page, flushes the invalid cache lines, and swaps a page from the auxiliary memory region to the first memory region.

Cache coherent support for flash in a memory hierarchy

In an embodiment, a system comprises a first memory module interface unit (MMIU) configured to couple to a first one or more memory modules, and a second MMIU configured to couple to a second one or more memory modules. The first MMIU is configured to operate the first one or more memory modules at a first frequency and the second MMIU is configured to concurrently operate the second one or more memory modules at a second operating frequency different from the first operating frequency.

Single interface access to multiple bandwidth and power memory zones

In an embodiment, an apparatus comprises one or more registers and a control unit coupled to the one or more registers. The control unit is configured to monitor a power state in one or more memory modules during execution of an application, and to store data generated during the monitoring in the one or more registers. In an embodiment, a system comprises a memory controller and a plurality of memory module interface units (MMIUs) coupled to the memory controller. Each of the plurality of MMIUs: is coupled to a respective plurality of memory modules; comprises one or more registers; is configured to monitor a power state in the respective plurality of memory modules during execution of an application; and is configured to store data generated during the monitoring in the one or more registers.

Memory power profiling

A memory subsystem is disclosed. The memory subsystem includes a memory controller coupled to one or more memory modules. Each memory module comprises a buffer coupled to one or more memory ranks. A clock source is coupled to provide a clock signal to each of the memory modules. The memory controller is configured to convey a clock enable (CKE) command to one of the memory modules, the CKE command corresponding to a given memory rank. In response to the CKE command, a memory module buffer associated with the given memory rank is configured to convey a CKE disable signal to the given memory rank. The given memory rank is configured to disable operation of the clock signal within the given memory rank, responsive to the CKE disable signal.

Clock enable throttling for power savings in a memory subsystem

A memory system is disclosed. The memory system includes a memory controller coupled to one or more memory modules, at least one of the memory modules including a buffer. The memory controller is configured to convey a command to at least one of the memory modules in response to detecting that no memory requests addressed to the at least one of the memory modules have been received during a specified window of time. In response to the command, the buffer of the at least one of the memory modules is configured to enter a reduced power state. The specified window of time may be either a specified number of memory refresh intervals or buffer sync intervals. The memory controller maintains a count of memory refresh or buffer sync intervals.

Power throttling in a memory system

Distinguishing between snoops initiated internally with respect to a processing unit and snoops initiated externally with respect to a processing unit allows maintenance of cache coherency for a processing unit with multiple independent cache nits. A processing unit with multiple independent cache units, issues an externally initiated snoop to its cache units. Responses from the multiple independent cache units are the basis for a unified response provided to at least the initiator of the external snoop. An internally initiated snoop is communicated to the host system, and communicated to peer cache unit(s) within the processing unit.

Cache coherency for multiple independent cache of a domain

A system for implementing a power management system in a computer system using a constant time reference to support an operating system. The system uses a PCI clock signal and a CPU clock signal to generate the constant time reference such that the operating system uses the constant time reference when the power management system causes the computer system's CPU frequency to change or when the CPU frequency has changed. The power management system comprises of circuitry to interface between normal power management system operations with that of the operations used to support the operating system.

Growing community of inventors

Cupertino, CA, United States of America

Sanjiv Kapil