Virage Logic Corporation

Sanjiv Kainth

Subramani Kengeri

Deepak Sabharwal

Prakash Ravikumar Bhatia

Shreekanth Sampigethaya

A method and system for testing the individual memory cells of a volatile memory cell array (e.g., SRAM) for data retention faults are described. In one embodiment of the invention, adjacent memory cells connected by a pair of common bit-lines are written with opposite, or complementary, data, for example, logical '0' and logical '1'. Next, the two memory cells are subjected to a stress condition by pre-charging the common bit-lines connecting the two adjacent memory cells, and then simultaneously asserting the word-line of each memory cell. Finally, the data in each cell is read and compared with the data written to the cell prior to generating the stress condition.

Method and system for accelerated detection of weak bits in an SRAM memory device

A multi-port memory device with an array of single-port memory cells is disclosed. According to one embodiment of the invention, the multi-port memory device has N number of memory ports, and is capable of performing any combination of N number of read/write operations during a single cycle of an externally generated core clock signal, without the need of any other externally generated clocking signals.

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New Delhi, India

Sanjiv Kainth