Intel Corporation

Sanjib Sarkar

Yun He

Narender R Nagulapally

Fei Deng

Senthil Arun Singaravelu

Pranali Shah

Adhiveeraraghavan Srikanth

Sriram Venkatesan

Subramaniam M Maiyuran

Mohammad A Abdallah

Varghese George

Vladimir M Pentkovski

Bruce Querbach

Ivan Herrera Mejia

Ruchira K Liyanage

Marina Sherman

Amjad M A Khan

Mir M Hossain

In accordance with embodiments disclosed herein, there is provided systems and methods for jitter sensing and adaptive control of parameters of clock and data recovery (CDR) circuits. A receiver component includes an adaptive CDR loop dynamic control circuit. The adaptive CDR loop dynamic control circuit is to detect first sinusoidal jitter at a first frequency and a first amplitude and update parameters of the CDR circuit to a first plurality of values based on the first frequency and the first amplitude. The adaptive CDR loop dynamic control circuit is further to detect second sinusoidal jitter at a second frequency and a second amplitude and update the parameters of the CDR circuit to a second plurality of values based on the second frequency and the second amplitude. The first sinusoidal jitter is in a first incoming data signal and the second sinusoidal jitter is in a second incoming data signal.

Jitter sensing and adaptive control of parameters of clock and data recovery circuits

A source device includes an adaptive link training circuity. The link training circuitry includes source capability information for link training of a link between the source device and a sink device. The source device includes a transmitter coupled to the adaptive link training circuitry to transmit the source capability information to the sink device. The adaptive link training circuitry is to initiate link training between the source device and the sink device, determine whether the link training between the source device and the sink device is unsuccessful, and in response to determining that the link training is unsuccessful, automatically adapt a setting of the link training based on the source capability information.

Adapt link training based on source capability information

A serial input/output method and receiver include an receiver portion to receive an analog differential serial input and sample the input to provide data and error signals, an equalization feedback loop responsive to the data and error signals to adjust the receiver portion, a phase feedback mechanism separate from the equalization feedback loop to provide a phase error, and a clock data recovery block coupled to receive the phase error to perform timing recovery for the receiver portion independent of the equalization feedback to adjust the sampling.

Unequalized clock data recovery for serial I/O receiver

Systems and methods of the present disclosure include transmitter devices. The transmitter devices include a high-speed driver domain having a low-dropout regulator. The low-dropout regulator reduces a voltage level from an input voltage source to the high-speed driver domain. In addition, the transmitter devices include a low-speed driver domain. The low-speed driver domain includes a pre-driver which reduces a voltage level from an input voltage source to the low-speed driver domain.

Multi-protocol support for display devices

Techniques for adaptive backchannel equalization. A total equalization value is determined over a preselected training period. A total balance equalization value is determined over the preselected training period. A transmitter equalization coefficient is determined based on the total equalization value and the total balance equalization value. Data is transmitted over a serial link using the transmitter equalization coefficient.

Adaptive backchannel equalization

Methods and apparatus related to adaptive control loop protection for fast and robust recovery from low-power states in high speed serial I/O applications are described. In some embodiments, a first bit pattern is detected, at a first agent, that indicates a speculative entry by a second agent into a low power consumption state and one or more control loops are frozen. A second bit pattern is detected (after entering the low power consumption state) that indicates exit from the low power consumption state by the second agent and the one or more control loops are unfrozen (e.g., in a specific order). Other embodiments are also claimed and/or disclosed.

Adaptive control loop protection for fast and robust recovery from low-power states in high speed serial I/O applications

A method and a processor may include storing a first set of data in a data array in a cache unit substantially concurrently to reading a second set of data from the data array, and using the second set of data to generate error correction data corresponding to the first set of data. A method or processor may include reading an entry from a cache in a processor and executing two or more error detection mechanisms on the entry substantially concurrently.

System and method for error correction in cache units

A technique includes in response to a training mode, communicating between a device and a processor of a computer system over a data bit line of a bus. The technique includes based on the communication, regulating a timing between a strobe signal and a signal that propagates over the data bit line.

Growing community of inventors

Folsom, CA, United States of America

Sanjib Sarkar