Apple Inc.

Cypress Semiconductor Corporation

Advanced Micro Devices Corporation

Nvidia Corporation

Globalfoundries Inc.

Sanjeev K Maheshwari

Emerson S Fang

Wenbo Liu

Brian S Leibowitz

Jafar Savoj

Jose A Tierno

Babak A Taheri

Lizhi Zhong

Vishal Varma

Bo Sun

Vishnu Balan

Meei-Ling Chiang

Wing Liu

Arif Al Amin

Ming-Shuan Chen

Gokce Gurun

Pradeep R Trivedi

Sumeet Gupta

Gin S Yee

Sunil Bhosekar

Gary A Rogan

Jaeduk Han

Dhaval H Shah

Fredrick B Jenne

Chintan S Thakkar

Charles L Wang

Dwight K Elvey

Haiming Jin

Gopal Patil

Ajay M Rao

Wei-Ming Lee

Yudong Zhang

Utkarsh Sharma

Sanjeev Aggarwal

An ADC with non-uniform quantization is disclosed. A SAR ADC includes a comparator configured to generate, during successive clock cycles, respective comparison signals based on an analog input signal and a corresponding offset voltage. The SAR ADC further includes a digital logic circuit configured to store values of the respective comparison signals for corresponding ones of the successive clock cycles and further configured to output a digital value after a specified number of successive clock cycles. An offset control circuit is configured to, for a current one of the successive clock cycles, generate the corresponding value of the offset voltage based on one or more of values of the respective comparison signals from previous clock cycles. Respective offset voltages for successive clock cycles are spaced such that the SAR ADC implements non-uniform quantization values.

ADC architecture with non-uniform quantization

A serial data receiver subsystem of a computer system includes a data rate detection circuit and a receiver circuit. The data rate detection circuit is configured to detect that a communication link operates in a high-speed mode rather than in a low-speed mode by detecting that a number of transitions in a serial data stream over a reference period of time exceeds a threshold value. The date rate detection circuit is further configured to activate a data rate detection signal indicating that the communication link operates in the high-speed mode, the data rate detection signal activated in response to detection that the number of transitions in the serial data stream over the reference period of time exceeds the threshold value. The receiver circuit is configured to activate one or more of a plurality of subcircuits included in the receiver circuit in response to activation of the data rate detection signal.

Data detection on serial communication links

The present disclosure describes a circuit that includes a first inductor circuit, a second inductor circuit, a first capacitor circuit, and a second capacitor circuit. The first inductor circuit includes a first inductor and a first driver circuit. The second inductor circuit includes a second inductor and a second driver circuit. The first inductor circuit operates at a first frequency. The second inductor operates at a second frequency. The first capacitor circuit provides a first signal to the second inductor circuit to adjust a first magnetic coupling generated by the first inductor circuit. The second capacitor circuit provides a second signal to the first inductor circuit to adjust a second magnetic coupling generated by the second inductor circuit.

Feedforward cancellation circuit

A serial data receiver subsystem included in a computer system may include a data detection circuit, a speed detection circuit, and a receiver circuit that includes multiple subcircuits. The data detection circuit performs a comparison of a reference voltage to the magnitude of signals received via a communication link that encodes a serial data stream consisting of multiple data symbols. Using a result of the comparison, the data detection circuit may activate a signal present indicator indicating the presence of data on the communication link. Once the signal present indicator is active, the speed detection circuit checks the number of transitions to determine a rate at which data is being transmitted. In response to a determination that the rate of the data being transmitted exceeds a threshold value, the receiver circuit activates one or more of the multiple subcircuits.

A phase detector circuit for use with a multi-level signaling communication protocol on a serial communication link is disclosed. The phase detector circuit employs multiple phase and logic circuits to detect data state changes between adjacent ones of voltage levels corresponding to different data states in the communication protocol, and generates early/late signals using the detected data state changes. The phase detector circuit statistically filters data state transitions between non-adjacent voltage levels to improve phase locking and reduce recovered clock jitter.

Phase detector circuit for multi-level signaling

A driver circuit for a serial communication bus employs multiple switch circuits to generate different voltage levels on a set of signal lines included in the serial communication bus. The different voltage levels correspond to different values for a set of bits to be transmitted via the serial communication bus. The driver circuit also employs a shunt circuit that couples at least two of the signals together in response to the set of bits matching a particular data pattern.

Serial communication link driver circuit with switchable shunt circuit

A decision feedback equalizer (DFE) sampler circuit is disclosed. The DFE sampler includes a front-end circuit configured to generate a filtered signal using a plurality of signals that encode a serial data stream that includes a plurality of data symbols and a summing circuit configured to generate an equalized signal by combining the filtered signal and an analog feedback signal based on a digital feedback signal. The DFE sampler further includes first and second samplers configured to sample the equalized signal and generate first and second regeneration signals, respectively, during first and second time periods. A compensation circuit is configured to generate the digital feedback signal using the first and second regeneration signals. The first and second samplers, in alternating time periods, cancel ISI from the equalized signal using the first and second regeneration signals, respectively.

Receiver with half-rate sampler circuits

To compensate for intersymbol interference, a serial data receiver circuit included in a computer system may include an equalizer circuit that includes a digital-to-analog converter circuit. Based on previously received symbols, the equalizer circuit modifies a signal received via a communication channel or link prior to clock and data recovery. In cases when the digital-to-analog converter circuit becomes saturated, the equalizer circuit additionally uses a dither signal to modify the received signal.

Serial data receiver circuit with dither assisted equalization

An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.

Serial data receiver with sampling clock skew compensation

A voltage regulator circuit included in a computer system may include a switch device coupled between an input power supply node and a regulated power supply node. The switch device may change a value of a supply current flowing from the input power supply node and the regulated power supply node to regulate a voltage level of the regulated power supply node. A noise cancelation current may be feed forward onto a control terminal of the switch device to cancel noise on the regulated power supply node resulting from noise present on the input power supply node.

Low dropout regulator with feedforward power supply noise rejection circuit

Embodiments relate to a circuit implementation for controlling a delay of a clock signal. The clock delay control circuit includes a sensing circuit and a phase interpolator controlled by the sensing circuit. The sensing circuit generates a first control signal that increases when a level of a supply voltage increases, and decreases when the level of the supply voltage decreases. Moreover, the sensing circuit generates a second control signal that decreases when the level of the supply voltage increases, and increases when the level of the supply voltage decreases. The phase interpolator includes multiple paths, each having a different propagation delay. The coupling between each path and the output node of the phase interpolator is controlled by the control signals generated by the sensing circuit.

On-chip supply ripple tolerant clock distribution

A multi-stage clock generation circuit is disclosed. The circuit includes first and second ring oscillators. The ring oscillators include a corresponding plurality of delay elements coupled in series, with a plurality of shunt circuits in parallel with corresponding inverters. The shunt circuits include respective interpolation nodes, which are resistively coupled to input and output nodes of their corresponding inverters. The interpolation nodes of the first ring oscillator are coupled to delay element input and output nodes of the second ring oscillator. Similarly, the interpolation nodes of the second ring oscillator are coupled to delay element input and output nodes of the first ring oscillator.

Multi-stage clock generator using mutual injection for multi-phase generation

A system and method for efficiently transporting data across lanes. A computing system includes an interconnect with lanes for transporting data between a source and a destination. When a source receives an indication of a bandwidth requirement change from a first data rate to a second data rate, the transmitter in the source sends messages to the receiver in the destination. The messages indicate that the data rate is going to change and reconfiguration of one or more lanes will be performed. The transmitter selects one or more lanes for transporting data at the second data rate. The transmitter maintains data transport at the first data rate while reconfiguring the selected one or more lanes to the second data rate. After completing the reconfiguration, the transmitter transports data at the second data rate on the selected one or more lanes while preventing data transport on any unselected lanes.

Growing community of inventors

Fremont, CA, United States of America

Sanjeev K Maheshwari