Cisco Technology, Inc.

Memoir Systems, Inc.

Avago Technologies International Sales Pte. Limited

Sanjeev Joshi

Sundar Iyer

Shang-Tse Chuang

Thu V Nguyen

Adam Kablanian

Shadab Nazar

Keith McCloghrie

Kartik Mohanram

Manjunath A G Gowda

Vinay Gaonkar

Ritesh Madapurath

Sachin Holla

One embodiment of the present invention provides a dynamic overlay tunnel orchestration system. During operation, the system detects the appearance of a first virtual machine running on a hypervisor of a first host machine coupled to a first switch in a network. The system identifies a first virtual local area network (VLAN) associated with the first virtual machine and determines whether an overlay tunnel exists between the first switch and a second switch coupling a second virtual machine belonging to the first VLAN. If no such overlay tunnel exists, the system generates an instruction for the first and second switches to establish a first overlay tunnel between the first and second switches.

Dynamic orchestration of overlay tunnels

Designing memory subsystems for integrated circuits can be time-consuming and costly task. To reduce development time and costs, an automated system and method for designing and constructing high-speed memory operations is disclosed. The automated system accepts a set of desired memory characteristics and then methodically selects different potential memory system design types and different implementations of each memory system design type. The potential memory system design types may include traditional memory systems, optimized traditional memory systems, intelligent memory systems, and hierarchical memory systems. A selected set of proposed memory systems that meet the specified set of desired memory characteristics is output to a circuit designer. When a circuit designer selects a proposed memory system, the automated system generates a complete memory system design, a model for the memory system, and a test suite for the memory system.

Hierarchical memory system compiler

An ActiveTest solution for memory is disclosed which can search for memory errors during the operation of a product containing digital memory. The ActiveTest system tests memory banks that are not being accessed by normal memory users in order to continually test the memory system in the background. When there is a conflict between the ActiveTest system and a memory user, the memory user is generally given priority.

Methods and apparatus for testing and repairing digital memory circuits

Multi-port memory circuits are often required within modern digital integrated circuits to store data. Multi-port memory circuits allow multiple memory users to access the same memory cell simultaneously. Multi-port memory circuits are generally custom-designed in order to obtain the best performance or synthesized with logic synthesis tools for quick design. However, these two options for creating multi-port memory give integrated circuit designers a stark choice: invest a large amount of time and money to custom design an efficient multi-port memory system or allow logic synthesis tools to inefficiently create multi-port memory. An intermediate solution is disclosed that allows an efficient multi-port memory array to be created largely using standard circuit cell components and register transfer level hardware design language code.

Methods and apparatus for synthesizing multi-port memory circuits

Controlling access to managed objects associated with a networked device. A method comprises receiving a request from a principal for access to a managed object associated with the networked device. The managed objects are accessible based on membership in access groups that are compliant with a Simple Network Management Protocol (SNMP). A first and a second of the access groups associated with the principal are determined. Access privileges for the principal are determined, based on the first and the second access groups. Access to the managed object is granted if permitted based on the access privileges for the principal.

Controlling access to managed objects in networked devices

Static random access memory (SRAM) circuits are used in most digital integrated circuits to store data. To handle multiple memory users, an efficient dual port six transistor (6T) SRAM memory cell is proposed. The dual port 6T SRAM cell uses independent word lines and bit lines such that the true side and the false side of the SRAM cell may be accessed independently. Single-ended reads allow the two independent word lines and bit lines to handle two reads in a single cycle using spatial domain multiplexing. Writes can be handled faster that read operations such that two writes can be handled in a single cycle using time division multiplexing. To further improve the operation of the dual port 6T SRAM cell a number of algorithmic techniques are used to improve the operation of the memory system.

Growing community of inventors

San Jose, CA, United States of America

Sanjeev Joshi