Everspin Technologies, Inc.

Texas Instruments Corporation

Other

University System of Maryland

Telcordia Technologies, Inc.

Everpsin Technologies, Inc.

Sanjeev Aggarwal

Kerry Joseph Nagel

Sarin A Deshpande

Jon Michael Slaughter

Nicholas David Rizzo

Kenneth H Smith

Scott Robert Summerfelt

Renu Whig

Chaitanya Mudivarthi

Jason A Janesky

Phillip G Mather

Jijun Sun

Moazzem Hossain

Thomas Andre

Theodore Sidney Moise

Syed M Alam

Stephen Roy Gilbert

Kelly Jay Taylor

Han-Jong Chia

Ramamoorthy Ramesh

Luigi Colombo

Dimitri Houssameddine

Lindsey H Hall

Sumio Ikegawa

Han Kyu Lee

Brian R Butcher

Frederick B Mancoff

Frederick Charles Neumeyer

Satyavolu Srinivas Papa Rao

Kaushal Kishore Singh

Renu Whig Dave

K R Udayakumar

Cristian P Masgras

Shimon

Hamid Almasi

Iftekhar Rahman

Pedro Sanchez

Scott Robert Perusse

J Scott Martin

Kevin M Conley

Stephan Grunow

Yaw S Obeng

John Anthony Rodriguez

Francis Gabriel Celii

Robert Kraft

Guoqiang Xing

Kezhakkedath Ramunni Udayakumar

Kelly Wayne Kyler

Trace Quentin Hurd

Chiu Chi

Anthony Ciancio

Philip Mather

Anil M Dhote

Wenchin Lin

Martin G Albrecht

Phillip Lopresti

Santosh Karre

Moazzern Hossain

Valli Arunachalam

Stevan G Hunter

Stevan Hunter

Tomojuki Sakoda

Sirisha Kuchimanchi

Jeff L Large

A method of manufacturing a magnetoresistive device may comprise forming a first magnetic region, an intermediate region, and a second magnetic region of a magnetoresistive stack above a via; removing at least a portion of the second magnetic region using a first etch; removing at least a portion of the intermediate region and at least a portion of the first magnetic region using a second etch; removing at least a portion of material redeposited on the magnetoresistive stack using a third etch; and rendering at least a portion of the redeposited material remaining on the magnetoresistive stack electrically non-conductive.

Magnetoresistive devices and methods of fabricating magnetoresistive devices

The present disclosure is drawn to, among other things, a method of managing a memory device. In some aspects, the method includes determining whether a first address for a page in a first memory region is mapped in a map table, setting a target address as a second address identified in the map table as being mapped to the first address, setting the target address as the first address, determining a number of bits that fail in each word of a plurality of first-layer error correction code (ECC) words for the target address, and adding the target address to the map table, writing-back contents from the target address to a repair address in the first memory region, and updating the map table by mapping the target address to the repair address.

Systems and methods for monitoring and managing memory devices

A memory device includes a printed circuit board, a magnetoresistive random-access memory (MRAM) device coupled to the printed circuit board, a controller or control circuitry, wherein the controller or control circuitry is integrated into, embedded in, or otherwise incorporated into the MRAM device, and a field programmable gate array (FPGA) coupled to the printed circuit board and in communication with the controller or control circuitry.

MRAM device with integrated controller for FPGA system and methods therefor

A method of manufacturing a magnetoresistive stack/structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer, (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.

Magnetoresistive stack/structure and method of manufacturing same

The present disclosure is drawn to, among other things, a configuration bit including at least four resistive elements and a voltage amplifier. At least two first resistive elements may be electrically connected in series via a first electrode and at least two second resistive elements may be electrically connected in series via a second electrode. The at least two first resistive elements may be electrically connected in parallel to the at least two second resistive elements via a third electrode and a fourth electrode. The first electrode and the second electrode may be electrically connected to a voltage supply. The third electrode and the fourth electrode may be electrically connected to an input of the voltage amplifier.

Systems and methods for configuration of a configuration bit with a value

The present disclosure is drawn to, among other things, a storage device. The storage device may include a magnetic tunnel junction (MTJ)-based storage array and a communication interface. The MTJ-based storage array may be configured to be damaged by a shorting voltage based on detection of a tamper event.

Cryptographic MRAM and methods thereof

A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes etching through a first portion of the magnetoresistive stack using a first etch process to form one or more sidewalls. At least a portion of the sidewalls includes redeposited material after the etching. The method also includes modifying at least a portion of the redeposited material on the sidewalls, and etching through a second portion of the magnetoresistive stack after the modifying step. The magnetoresistive stack may include a first magnetic region, an intermediate region disposed over the first magnetic region, and a second magnetic region disposed over the intermediate region.

Method of manufacturing integrated circuit using encapsulation during an etch process

The present disclosure is drawn to, among other things, a magnetoresistive device and a magnetoresistive memory comprising a plurality of such magnetoresistive devices. In some aspects, a magnetoresistive device may include a magnetically fixed region, a magnetically free region above or below the magnetically fixed region, and an intermediate region positioned between the magnetically fixed region and the magnetically free region, wherein the intermediate region includes a first dielectric material. The magnetoresistive device may also include encapsulation layers formed on opposing side walls of the magnetically free region, wherein the encapsulation layers include the first dielectric material.

Magnetoresistive stack/structure and methods therefor

A magnetoresistive stack/structure and method of manufacturing same comprising wherein the stack/structure includes a seed region, a fixed magnetic region disposed on and in contact with the seed region, a dielectric layer(s) disposed on the fixed magnetic region and a free magnetic region disposed on the dielectric layer(s). In one embodiment, the seed region comprises an alloy including nickel and chromium having (i) a thickness greater than or equal to 40 Angstroms (+/−10%) and less than or equal to 60 Angstroms (+/−10%), and (ii) a material composition or content of chromium within a range of 25-60 atomic percent (+/−10%) or 30-50 atomic percent (+/−10%).

Magnetoresistive stack with seed region and method of manufacturing the same

Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.

Methods of forming magnetoresistive devices and integrated circuits

Fabrication of a magnetic memory element, including a via () in an interlevel dielectric layer (), providing an electrical connection between an underlying metal region () and a magnetoresistive stack device, such as a magnetic tunnel junction (), involves forming a transition metal layer () in the via by atomic layer deposition. The via optionally includes a tantalum-rich layer () above, and/or a cap layer () below, the transition metal layer, and may have a diameter less than or equal than a diameter of the magnetoresistive stack device.

Methods for manufacturing magnetoresistive stack devices

A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes. For example, an exemplary method of manufacturing a magnetoresistive device includes etching through a second electrode, second dielectric layer and free magnetic layer to provide a sidewall of (i) an unpinned synthetic antiferromagnetic structure, (ii) a second dielectric layer and (iii) a free magnetic layer; thereafter, forming an encapsulation material on the sidewall of the unpinned synthetic antiferromagnetic structure, second dielectric layer and free magnetic layer, and after forming the encapsulation material, etching through a first dielectric layer.

Magnetoresistive structure having two dielectric layers, and method of manufacturing same

Growing community of inventors

Scottsdale, AZ, United States of America

Sanjeev Aggarwal